Liquid crystal display device

ABSTRACT

Each of pixels arranged in a matrix has at least first and second subpixels defined to include an electrode pair of a subpixel electrode and a counter electrode facing each other with a liquid crystal layer interposed therebetween. A scanning signal is applied from a scanning signal line of each row of the matrix to a gate electrode of a TFT for applying a data signal from a source signal line to the subpixel electrode included in each of the first and second subpixels. A discharge capacitor electrode is connected to the subpixel electrode of the second subpixel through another TFT. When the signal width of the scanning signal is within a range from M times (M is 0 or 1) the length of 1 H to (M+1) times, a discharge signal line is connected to the scanning signal line, which is scanned after N horizontal scanning periods (N is M+2, that is, 2 or 3), by a signal-to-signal connection line.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.15/753,951 filed Feb. 20, 2018, which application is the national phaseunder 35 U. S. C. § 371 of PCT International Application No.PCT/JP2015/074294 which has an International filing date of Aug. 27,2015 and designated the United States of America.

FIELD

The present invention relates to a liquid crystal display device, and inparticular, to a liquid crystal display device for improving the viewingangle dependence of the gamma characteristics.

BACKGROUND

The liquid crystal display device is a flat display device havingexcellent features, such as high definition, thin shape, light weight,and low power consumption, and is widely used for a flat TV, a PCmonitor, a digital signage, and the like.

A twisted nematic (TN) mode liquid crystal display device that has beenconventionally used in general is excellent in productivity, but has aproblem in viewing angle characteristics relevant to screen display. Forexample, when the display screen is viewed from an oblique directionwith respect to the normal line, the contrast ratio is significantlyreduced and the brightness difference between gradations issignificantly unclear in the TN mode liquid crystal display device. Inaddition, a so-called gradation inversion phenomenon may be observed inwhich a portion that looks bright (or dark) when the display screen isviewed from the front looks dark (or bright) when the display screen isviewed from an oblique direction with respect to the normal line.

As liquid crystal display devices for solving the problem of the viewingangle characteristics described above, there are liquid crystal displaydevices that perform display in display modes, such as an in-planswitching (IPS) mode and a multi domain vertical alignment (MVA) mode.Techniques for realizing the display modes in these liquid crystaldisplay devices are widely used as techniques for improving the viewingangle characteristics.

Incidentally, one of problems of the viewing angle characteristics isthat the gamma characteristics indicating the gradation dependence ofthe display brightness depend on the angle of the line of sight withrespect to the normal line of the display screen (hereinafter, referredto as the viewing angle dependence of the gamma characteristics). Thisproblem is that the gradation display state differs depending on theobservation direction with respect to the display screen and accordinglythe gamma characteristics are differently observed between a case wherethe observation direction is a direction along the normal line of thedisplay screen and a case where the observation direction is an obliquedirection with respect to the normal line of the display screen.

On the other hand, Non-Patent Document 1 (Sang Soo Kim, Bong Hyun You,Jung Hwan Cho, Sung Jae Moon, Brian H. Berkeley and Nam Deog Kim, ‘82″Ultra Definition LCD Using New Driving Scheme and Advanced Super PVATechnology’, SID Symposium Digest of Technical Papers, May 2008, Volume39, Issue 1, p. 196-199) discloses a liquid crystal display device forimproving the viewing angle dependence (referred to as viewing angledependence in some documents) of the gamma characteristics. In theliquid crystal display device disclosed in Non-Patent Document 1, eachpixel is configured to include first and second subpixels, and adischarge capacitor (Cdown) is provided in the second subpixel. Subpixelelectrodes of the first and second subpixels are connected to datasignal lines (source signal lines), which are different alternately forrespective pixels in the vertical direction of the display screen,through TFT1 and TFT2 having control electrodes to which a scanningsignal (gate signal) is applied from the scanning signal line, and twolines are simultaneously scanned. In the discharge capacitor, adischarge capacitor electrode facing a counter electrode is connected tothe subpixel electrode of the second subpixel through a TFT3. Inaddition, a discharge signal line for applying a discharge signal to thecontrol electrode of the TFT3 is connected to the scanning signal linebehind two lines.

In the liquid crystal display device disclosed in Non-Patent Document 1,for each pixel, a discharge signal delayed by one horizontal scanningperiod (1 H) from the scanning signal for each pixel is applied to thecontrol electrode of the TFT3. By connecting the discharge capacitorelectrode and the subpixel electrode of the second subpixel according tothe signal delayed by 1 H from the scanning signal in this manner, theeffective voltage applied to the liquid crystal layer by each of thefirst and second subpixels can be changed. In this case, since eachpixel is observed in a state in which the gamma characteristics that aredifferent for respective subpixels are harmonized, the viewing angledependence of the gamma characteristics is improved.

A liquid crystal display device disclosed in U.S. Pat. No. 8,952,877 isconfigured such that each pixel includes first and second subpixels,each of which has a subpixel electrode, similarly to the liquid crystaldisplay device disclosed in Non-Patent Document 1, and a dischargecapacitor (Cdown) is connected to the subpixel electrode of the secondsubpixel through a third TFT (corresponding to the TFT3 describedabove). Similarly to the case of Non-Patent Document 1, subpixelelectrodes of the first and second subpixels are connected to datasignal lines, which are different alternately for respective pixels,through first and second TFTs (corresponding to the TFT1 and the TFT2described above), and two lines are simultaneously scanned. The controlelectrodes (gates) of the first and second TFTs are connected to a gateline (corresponding to the scanning signal line described above), andthe control electrode of the third TFT is connected to a charge controlline (corresponding to the discharge signal line described above).

In the liquid crystal display device disclosed in U.S. Pat. No.8,952,877, for the two lines scanned simultaneously, gate lines areconnected to each other through a gate connection line, and chargecontrol lines are connected to each other through a charge connectionline. Since these connections are made within the liquid crystal panel,the gate connection line and the charge connection line intersect witheach other within the liquid crystal panel. The charge connection lineis connected to a gate connection line for two lines scanned 1 H laterthan the above two lines. By such a connection, similarly to the liquidcrystal display device disclosed in Non-Patent Document 1, a signal(corresponding to a discharge signal) delayed by 1 H from the scanningsignal for each pixel is applied to the control electrode of the thirdTFT and the subpixel electrode of the second subpixel is connected tothe discharge capacitor. As a result, the effective voltage applied tothe liquid crystal layer by the second subpixel changes.

Incidentally, it is known that, in the TFT, due to the influence of theparasitic capacitance between the gate and the drain, a feed-throughvoltage (so-called pull-in voltage) is generated at the falling time ofthe driving voltage for the gate and the voltage of the drain (that is,the voltage of the subpixel electrode) drops. In addition to thisphenomenon, due to the influence of another parasitic capacitancepresent between each subpixel electrode and the discharge signal line(or the charge control line), in particular, a phenomenon may beobserved in which the voltage of the subpixel electrode of the firstsubpixel slightly rises and drops at the rising time and falling time ofthe discharge signal of the previous line.

For example, in a case where there is no signal overlap between thescanning signal and the discharge signal of the previous line,influences at the rising time and the falling time are appropriatelycanceled out in each subpixel electrode. For this reason, theabove-described phenomenon is difficult to observe.

SUMMARY

However, in the liquid crystal display devices disclosed in Non-PatentDocument 1 and U.S. Pat. No. 8,952,877, in two lines scannedsimultaneously, the first subpixel of the first line is influenced bythe discharge signal of the previous line that is turned on at the sametiming as the scanning signal of the first line, and the first subpixelof the second line is influenced by the discharge signal of the firstline that rises at substantially the same timing as the falling edge ofthe scanning signal of the second line.

Therefore, in any first subpixel, there is a possibility that theinfluences of rising and falling of the voltage of the subpixelelectrode occurring at the rising time and the falling time of thedischarge signal are not sufficiently canceled out. For this reason,there is a problem that a counter voltage, which is optimal for thecounter electrode that the subpixel electrode faces, deviates from apreset counter voltage (hereinafter, referred to as counter voltagedeviation).

The present invention has been made in view of the above circumstances,and it is an object of the present invention to provide a liquid crystaldisplay device capable of preventing a counter voltage, which is optimalfor a counter electrode that a subpixel electrode included in a pixelfaces, from deviating from a preset counter voltage.

In a liquid crystal display device according to the present invention,pixels each of which has at least first and second subpixels defined toinclude an electrode pair of a subpixel electrode and a counterelectrode facing each other with a liquid crystal layer interposedtherebetween are arranged in a matrix. The liquid crystal display deviceincludes: first and second switching elements for applying a data signalto subpixel electrodes included in the first and second subpixels; ascanning signal line for applying a scanning signal to controlelectrodes of the first and second switching elements for each row ofthe matrix; an electrode pair of a discharge capacitor electrodeincluded in the second subpixel and a discharge capacitor counterelectrode connected to a predetermined potential; a third switchingelement connected between the discharge capacitor electrode and thesubpixel electrode of the second subpixel; and a discharge signal linefor applying a discharge signal for turning on the third switchingelement to a control electrode of the third switching element for eachrow of the matrix. The signal width of the scanning signal is longerthan M times (M is an integer of 0 or more) the length of one horizontalscanning period and shorter than (M+1) times, and a signal-to-signalconnection line connecting the discharge signal line to a scanningsignal line of a row, which is scanned after N horizontal scanningperiods (N is an integer of M+2 or more), is provided.

In the liquid crystal display device according to the present invention,the first and second subpixels are arranged in a direction crossing thedischarge signal line, and the discharge signal line is arranged betweenadjacent first and second subpixels in pixels adjacent to each other inthe direction.

In the liquid crystal display device according to the present invention,the polarity of a data signal applied to the first and second subpixelsis inverted every frame period.

In the liquid crystal display device according to the present invention,the signal width of the scanning signal is longer than a length obtainedby subtracting a predetermined time from (M+1) times the length of onehorizontal scanning period, and the signal-to-signal connection line isconnected to a scanning signal line of a row scanned after L horizontalscanning periods (L is an integer of M+3 or more).

In the liquid crystal display device according to the present invention,each of the first and second subpixels is defined to include anelectrode pair of an auxiliary capacitor electrode connected to thesubpixel electrode and an auxiliary capacitor counter electrodeconnected to the predetermined potential.

In the liquid crystal display device according to the present invention,the pixel is defined to include an electrode pair having electrodesconnected to the discharge capacitor electrode and the subpixelelectrode of the first subpixel.

The liquid crystal display device according to the present inventionfurther includes a liquid crystal panel in which the scanning signalline and the signal-to-signal connection line are wired in an edgeportion, and the signal-to-signal connection line intersects with (N−1)scanning signal lines.

The liquid crystal display device according to the present inventionfurther includes two data signal lines for applying data signals, whichare different alternately for respective rows of the matrix, to one endof each of the first and second switching elements for each column ofthe matrix, and two adjacent rows are simultaneously scanned.

The liquid crystal display device according to the present inventionfurther includes a liquid crystal panel in which the scanning signalline and the signal-to-signal connection line are wired in an edgeportion, and the signal-to-signal connection line intersects with (2N−1)scanning signal lines.

The liquid crystal display device according to the present inventionfurther includes: a scanning signal connection line connecting scanningsignal lines to each other for the two rows and a discharge signalconnection line connecting discharge signal lines to each other for thetwo rows; a common scanning signal line for applying a scanning signalcommon to the two rows to the scanning signal connection line; and aliquid crystal panel in which the signal-to-signal connection line andthe common scanning signal line are wired in an edge portion. Thesignal-to-signal connection line is wired in common to the two rows, andintersects with (N−1) common scanning signal lines.

In the present invention, each of the pixels arranged in a matrix has atleast the first and second subpixels defined to include an electrodepair of the subpixel electrode and the counter electrode facing eachother with the liquid crystal layer interposed therebetween, and thescanning signal is applied from the scanning signal line of each row(that is, each line) of the matrix to the control electrodes of thefirst and second switching elements for applying the data signal to thesubpixel electrode included in each of the first and second subpixels.The discharge capacitor electrode is connected to the subpixel electrodeof the second subpixel through the third switching element, and thedischarge capacitor counter electrode connected to the predeterminedpotential faces the discharge capacitor electrode. The signal width ofthe scanning signal is within a range from M times (M is an integer of 0or more) the length of one horizontal scanning period to (M+1) times,and the discharge signal line for applying the discharge signal to eachline is connected to the scanning signal line of a row, which is scannedafter N horizontal scanning periods (N is an integer of M+2 or more), bythe signal-to-signal connection line.

Therefore, after a point in time at which no data signal is applied tothe subpixel electrodes of the first and second subpixels of each line,the discharge signal is applied to the control electrode of the thirdswitching element of the previous line. As a result, for the voltageapplied to the liquid crystal layer by the first and second subpixelsthat the pixel of each line has at least, influences of the rising andfalling of the discharge signal of the previous line are canceled out.

In the present invention, the arrangement direction of the first andsecond subpixels is a direction crossing the discharge signal line, andthe discharge signal line is arranged between adjacent first and secondsubpixels in adjacent pixels.

Therefore, when the scanning signal line is arranged at a positionoverlapping each pixel, leakage of a signal between the discharge signalline and the scanning signal line is suppressed.

In the present invention, the polarity of the data signal applied toeach pixel is inverted every frame. Therefore, the voltage of thesubpixel electrode of the second subpixel is effectively changed whenthe third switching element is turned on, so that the contrastdifference between the two subpixels increases.

In the present invention, the signal width of the scanning signal islonger than a length, which is obtained by subtracting a predeterminedtime from (M+1) times (M is an integer of 0 or more) the length of onehorizontal scanning period, and shorter than (M+1) times the length ofone horizontal scanning period, and the discharge signal line isconnected to the scanning signal line of a row, which is scanned after Lhorizontal scanning periods (L is an integer of M+3 or more), by thesignal-to-signal connection line.

Therefore, since the discharge signal line is connected to the scanningsignal line behind L lines, which is scanned after L horizontal scanningperiods (L is an integer larger by 1 than the above N), application ofthe discharge signal to the control electrode of the third switchingelement of the previous line within a predetermined time from the pointin time at which no data signal is applied to the subpixel electrodes ofthe first and second subpixels of each line is avoided.

In the present invention, an electrode pair defining each of the firstand second subpixels of the pixel includes an electrode pair of theauxiliary capacitor electrode and the auxiliary capacitor counterelectrode, the auxiliary capacitor electrode is electrically connectedto the subpixel electrode, and the auxiliary capacitor counter electrodeis connected to the predetermined potential that is the connectiondestination of the discharge capacitor counter electrode.

Therefore, since the auxiliary capacitor formed by the auxiliarycapacitor electrode and the auxiliary capacitor counter electrode isconnected in parallel to the liquid crystal capacitor formed by thesubpixel electrode and the counter electrode of each of the first andsecond subpixels, the voltage applied to the liquid crystal layer by thefirst and second subpixels is stably held for at least one frame period.

In the present invention, when the third switching element is turned on,a part of charges accumulated in the second subpixel move to the firstsubpixel through the electrode pair having electrodes respectivelyconnected to the discharge capacitor electrode and the subpixelelectrode of the first subpixel.

Therefore, the voltages of the subpixel electrodes of the first andsecond subpixels change in opposite polarities.

In the present invention, at least the scanning signal line and thesignal-to-signal connection line are wired in the edge portion of theliquid crystal panel, and the signal-to-signal connection lineintersects with (N−1) scanning signal lines at the edge portion of theliquid crystal panel.

That is, the signal-to-signal connection line connects the dischargesignal line and the scanning signal line behind N lines, which isscanned after N horizontal scanning periods, to each other in aone-to-one manner. Accordingly, when the signal-to-signal connectionline is wired in the edge portion on one side of the liquid crystalpanel and the scanning signal is applied to each scanning signal line ofeach row from the same one side, the signal-to-signal connection lineand (N−1) scanning signal lines inevitably intersect with each other atthe edge portion on one side of the liquid crystal panel.

In the present invention, data signals that are different alternatelyfor respective lines are applied from two data signal lines, which arearranged for each column of the matrix, to the subpixel electrodes ofthe first and second subpixels through the first and second switchingelements, and the scanning signals of two adjacent lines aresimultaneously turned on. Therefore, two lines are scanned within onehorizontal scanning period.

In the present invention, the scanning signal line and thesignal-to-signal connection line are wired in the edge portion of theliquid crystal panel, and the signal-to-signal connection lineintersects with (2N−1) scanning signal lines at the edge portion of theliquid crystal panel.

That is, the signal-to-signal connection line connects the dischargesignal line and the scanning signal line behind 2N lines, which isscanned after N horizontal scanning periods, to each other in aone-to-one manner. Accordingly, when the signal-to-signal connectionline is wired in the edge portion on one side of the liquid crystalpanel and the scanning signal is applied to each scanning signal linefrom the same one side, the signal-to-signal connection line and (2N−1)scanning signal lines inevitably intersect with each other at the edgeportion on one side of the liquid crystal panel.

In the present invention, the scanning signal lines are connected toeach other by the scanning signal connection line and the dischargesignal lines are connected to each other by the discharge signalconnection line for two rows scanned simultaneously, and the commonscanning signal line for applying the scanning signal to the scanningsignal connection line and the signal-to-signal connection lineconnecting the discharge signal connection line and the scanning signalconnection line to each other are wired in the edge portion of theliquid crystal panel. In addition, the signal-to-signal connection lineintersects with (N−1) common scanning signal lines at the edge portionof the liquid crystal panel.

That is, the signal-to-signal connection line connects the dischargesignal connection line and the scanning signal connection line, whichmakes a connection between two lines scanned after N horizontal scanningperiods, to each other in a one-to-one manner. Accordingly, when thesignal-to-signal connection line is wired in the edge portion on oneside of the liquid crystal panel and the scanning signal is applied toeach common scanning signal line from the same one side, thesignal-to-signal connection line and (N−1) common scanning signal linesinevitably intersect with each other at the edge portion on one side ofthe liquid crystal panel.

According to the present invention, after a point in time at which nodata signal is applied to the subpixel electrodes of the first andsecond subpixels of each line, the discharge signal is applied to thethird switching element of the previous line. As a result, for thevoltage applied to the liquid crystal layer by the first and secondsubpixels that the pixel of each line has at least, influences of therising and falling of the discharge signal of the previous line arecanceled out.

Therefore, it is possible to prevent the counter voltage, which isoptimal for the counter electrode that the subpixel electrode includedin the pixel faces, from deviating from the preset counter voltage.

The above and further objects and features will more fully be apparentfrom the following detailed description with accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating an example of the configurationof a liquid crystal display device according to Embodiment 1 of thepresent invention.

FIG. 2 is an explanatory diagram schematically illustrating aconfiguration for defining a pixel in the liquid crystal display deviceaccording to Embodiment 1.

FIG. 3 is a cross-sectional view schematically illustrating theconfiguration of a liquid crystal panel.

FIG. 4 is an explanatory diagram illustrating a parasitic capacitanceassociated with a pixel.

FIG. 5 is a timing chart illustrating temporal changes of a signalapplied to each signal line and the voltage of a subpixel electrode.

FIG. 6A is a timing chart illustrating temporal changes of a signalapplied to each signal line and the voltage of a subpixel electrode inthe liquid crystal display device according to Embodiment 1.

FIG. 6B is a timing chart illustrating temporal changes of a signalapplied to each signal line and the voltage of a subpixel electrode inthe liquid crystal display device according to Embodiment 1.

FIG. 7 is an explanatory diagram illustrating a connection example of asignal-to-signal connection line in a liquid crystal panel according toModification Example 1 of Embodiment 1.

FIG. 8 is a timing chart illustrating temporal changes of a scanningsignal and a discharge signal in the liquid crystal panel according toModification Example 1 of Embodiment 1.

FIG. 9 is a block diagram illustrating an example of the configurationof a liquid crystal display device according to Modification Example 2of Embodiment 1.

FIG. 10 is an explanatory diagram schematically illustrating aconfiguration for defining a pixel in a liquid crystal panel accordingto Modification Example 2 of Embodiment 1.

FIG. 11 is an explanatory diagram schematically illustrating aconfiguration for defining a pixel in a liquid crystal panel accordingto Modification Example 3 of Embodiment 1.

FIG. 12 is a block diagram illustrating an example of the configurationof a liquid crystal display device according to Embodiment 2 of thepresent invention.

FIG. 13 is an explanatory diagram illustrating the connectionrelationship between a pixel and a source signal line.

FIG. 14A is a timing chart illustrating temporal changes of a signalapplied to each signal line and the voltage of a subpixel electrode inthe liquid crystal display device according to Embodiment 2.

FIG. 14B is a timing chart illustrating temporal changes of a signalapplied to each signal line and the voltage of a subpixel electrode inthe liquid crystal display device according to Embodiment 2.

FIG. 15 is a graph showing the relationship between the delay time of adischarge signal and an optimum counter voltage.

FIG. 16 is an explanatory diagram for describing the presence or absenceof horizontal streaks caused by counter voltage deviation.

FIG. 17 is an explanatory diagram illustrating a connection example of asignal-to-signal connection line in a liquid crystal panel according toModification Example 4 of Embodiment 2.

FIG. 18 is a timing chart illustrating temporal changes of a scanningsignal and a discharge signal in the liquid crystal panel according toModification Example 4 of Embodiment 2.

FIG. 19 is a graph showing the relationship between the connectiondestination of a discharge signal line and an optimum counter voltagedifference.

FIG. 20 is a block diagram illustrating an example of the configurationof a liquid crystal display device according to Modification Example 5of Embodiment 2.

FIG. 21 is an explanatory diagram illustrating a connection example of asignal-to-signal connection line in a liquid crystal panel according toModification Example 5 of Embodiment 2.

DETAILED DESCRIPTION

Hereinafter, the present invention will be described in detail withreference to the diagrams illustrating its embodiments.

Embodiment 1

FIG. 1 is a block diagram illustrating an example of the configurationof a liquid crystal display device according to Embodiment 1 of thepresent invention, and FIG. 2 is an explanatory diagram schematicallyillustrating a configuration for defining a pixel P in the liquidcrystal display device according to Embodiment 1. The liquid crystaldisplay device illustrated in FIG. 1 includes a liquid crystal panel 100a in which the pixels P, each of which has at least two subpixelsdefined to include an electrode pair to be described later, are arrangedin a matrix in a vertical direction (hereinafter, also referred to as arow direction) and a horizontal direction (hereinafter, also referred toas a column direction) of the display screen. In FIG. 1, fourconsecutive pixels P in the row direction and signal lines relevant tothe pixels P are mainly illustrated. In the following description, it isassumed that a pair of electrodes other than a pair of electrodes facingeach other with a liquid crystal layer 3 interposed therebetween faceeach other with an insulating layer (not illustrated) interposedtherebetween to form an electrostatic capacitance (capacitor).

In FIG. 2, the pixel P has at least a subpixel SP1 (corresponding to afirst subpixel) and a subpixel SP2 (corresponding to a second subpixel)divided in the vertical direction of the display screen of the liquidcrystal panel 100 a. The subpixel SP1 is defined to include an electrodepair of a subpixel electrode 11 a and a counter electrode 21, which faceeach other with the liquid crystal layer 3 interposed therebetween, andan electrode pair of an auxiliary capacitor electrode 12 a and anauxiliary capacitor counter electrode 22 a. A drain electrode of a thinfilm transistor (TFT: corresponding to a first switching element) 15 ais connected to the subpixel electrode 11 a. The subpixel electrode 11 aand the auxiliary capacitor electrode 12 a are electrically connected toeach other. The auxiliary capacitor counter electrode 22 a is connectedto the potential (corresponding to a predetermined potential) of thecounter electrode 21. A liquid crystal capacitor Clc1 is formed by thesubpixel electrode 11 a and the counter electrode 21. In addition, anauxiliary capacitor Ccs1 is formed by the auxiliary capacitor electrode12 a and the auxiliary capacitor counter electrode 22 a.

The subpixel SP2 is defined to include an electrode pair of a subpixelelectrode 11 b and a counter electrode 21 facing each other with theliquid crystal layer 3 interposed therebetween, an electrode pair of anauxiliary capacitor electrode 12 b and an auxiliary capacitor counterelectrode 22 b, and an electrode pair of a discharge capacitor electrode13 and a discharge capacitor counter electrode 23. A drain electrode ofa TFT (corresponding to a second switching element) 15 b is connected tothe subpixel electrode 11 b. The subpixel electrode 11 b and theauxiliary capacitor electrode 12 b are electrically connected to eachother. The discharge capacitor electrode 13 is connected to the subpixelelectrode 11 b through a TFT (corresponding to a third switchingelement) 14. The auxiliary capacitor counter electrode 22 b and thedischarge capacitor counter electrode 23 are connected to the potentialof the counter electrode 21. The counter electrode 21 is common to thesubpixels SP1 and SP2. However, the present invention is not limitedthereto. A liquid crystal capacitor Clc2 is formed by the subpixelelectrode 11 b and the counter electrode 21. An auxiliary capacitor Ccs2is formed by the auxiliary capacitor electrode 12 b and the auxiliarycapacitor counter electrode 22 b. In addition, a discharge capacitor Cdcis formed by the discharge capacitor electrode 13 and the dischargecapacitor counter electrode 23. In addition, the ratio of the sizes ofthe subpixel electrode 11 a and the subpixel electrode 11 b is notlimited to 1:1, and the number of subpixels is not limited to two.

On one side of the pixel P in the horizontal direction, a source signalline (corresponding to a data signal line) SL for applying a sourcesignal (corresponding to a data signal) to the subpixel electrodes 11 aand 11 b through the TFTs 15 a and 15 b, respectively, is linearlyarranged in the vertical direction. Source electrodes of TFTs 15 a and15 b are connected to the source signal line SL. Gate electrodes(corresponding to control electrodes) of the TFTs 15 a and 15 b areconnected to a scanning signal line Gm that is linearly arranged so asto horizontally cross the central portion of the pixel P. The gateelectrode of the TFT 14 is connected to a discharge signal line Gs thatis linearly arranged so as to horizontally cross between the currentpixel P and the pixel P in the next row (hereinafter, a row is alsoreferred to as a line) adjacent to the current pixel P in the verticaldirection (row direction). The scanning signal line Gm and the dischargesignal line Gs are provided row by row in the row direction of thematrix. Since the scanning signal line Gm and the discharge signal lineGs of respective rows are appropriately spaced apart from each other,leakage of a signal between the scanning signal line Gm and thedischarge signal line Gs is suppressed.

Returning to FIG. 1, in an edge portion 101 a on one side, among edgeportions excluding a display region (region surrounded by the brokenline in the diagram) where the pixels P are arranged in the liquidcrystal panel 100 a, signal-to-signal connection lines Wsm connectingeach discharge signal line Gs to the scanning signal line Gm behind twolines, which is scanned after two horizontal scanning periods, areseparately wired. In the edge portion 101 a, the scanning signal line Gmextending from the display region is wired. The signal-to-signalconnection line Wsm intersects with one scanning signal line Gm at theedge portion 101 a.

In addition, the liquid crystal display device according to Embodiment 1includes a gate driver GDa for applying a scanning signal to scanningsignal lines Gm, Gm, . . . , Gm and applying a discharge signal todischarge signal lines Gs, Gs, . . . , Gs, a source driver SDa forapplying a source signal to source signal lines SL, SL, . . . , SL, anda display control circuit 4 a for controlling the display of the liquidcrystal panel 100 a using the gate driver GDa and the source driver SDa.

The display control circuit 4 a has an image signal input circuit 40 forreceiving an image signal including image data indicating an image and ascanning signal control circuit 42 a and a source signal control circuit41 a for controlling the gate driver GDa and the source driver SDa,respectively, based on a clock signal and a synchronization signalseparated by the image signal input circuit 40.

The scanning signal control circuit 42 a and the source signal controlcircuit 41 a generate control signals such as a start signal, a clocksignal, and an enable signal, which are required for the periodicoperations of the gate driver GDa and the source driver SDa. Inaddition, the source signal control circuit 41 a outputs digital imagedata separated by the image signal input circuit 40 to the source driverSDa.

The gate driver GDa sequentially applies scanning signals to thescanning signal lines Gm, Gm, . . . , Gm in one horizontal scanningperiod within one frame period of the image data. The source driver SDagenerates an analog source signal (parallel signal) indicating an imageof one line by accumulating the digital image data (serial data) givenfrom the source signal control circuit 41 a in one horizontal scanningperiod (1 H), and applies the generated source signal in parallel to thesource signal lines SL, SL, . . . , SL of respective columns. Here, thesource signal of one line is updated every horizontal scanning period.

The scanning signal applied to one of the scanning signal lines Gm, Gm,. . . , Gm is applied to the gate electrodes of the TFTs 15 a and 15 bincluded in each of the pixels P, P, . . . , P of one line arranged inthe column direction. A discharge signal is applied from the dischargesignal lines Gs, Gs, . . . , Gs to the gate electrode of the TFT 14included in each of the pixels P, P, . . . , P of the one line. Thedischarge signal of each line is delayed by two horizontal scanningperiods with respect to the scanning signal of each line.

In one horizontal scanning period in which a scanning signal is appliedto one scanning signal line Gm, the source signal applied to the sourcesignal lines SL, SL, . . . , SL is applied to the subpixel electrodes 11a and 11 b through the TFTs 15 a and 15 b, of which gate electrodes areconnected to the above one scanning signal line Gm, respectively, and isalso applied to the auxiliary capacitor electrodes 12 a and 12 b. As aresult, a source signal is written into the liquid crystal capacitorsClc1 and Clc2 and the auxiliary capacitors Ccs1 and Ccs2 that are formedin the subpixels SP1 and SP2, respectively. In this manner, the sourcesignal of one line is simultaneously written into the pixels P, P, . . ., P of one line in one horizontal scanning period. The source signalwritten into the subpixels SP1 and SP2 is held for one frame periodunless there is a change in the combined capacitance.

Next, the optical configuration of the liquid crystal panel 100 a andthe optical configuration of another liquid crystal panel that canreplace the liquid crystal panel 100 a will be described.

FIG. 3 is a cross-sectional view schematically illustrating theconfiguration of the liquid crystal panel 100 a. The liquid crystalpanel 100 a is configured by interposing the liquid crystal layer 3between a first glass substrate (array substrate) 1 and a second glasssubstrate 2. Between the opposite surfaces of the first glass substrate1 and the second glass substrate 2, a sealing material 33 for sealingliquid crystal to be sealed in the liquid crystal layer 3 is providedalong the peripheral edge portion of the second glass substrate 2.

On one surface of the first glass substrate 1, an alignment film 31 isformed on a layer including the subpixel electrodes 11 a and 11 b, theauxiliary capacitor electrodes 12 a and 12 b, the auxiliary capacitorcounter electrodes 22 a and 22 b, the discharge capacitor electrode 13,and the discharge capacitor counter electrode 23, which are transparentelectrodes, the TFT 14, and the TFTs 15 a and 15 b. A polarizing plate19 is bonded to the other surface of the first glass substrate 1. Aflexible substrate 18 on which the gate driver GDa is surface-mounted isattached to one edge portion of the one surface of the first glasssubstrate 1.

On one surface of the second glass substrate 2, the counter electrode 21that is a transparent electrode and an alignment film 32 are laminatedand formed. In particular, in the liquid crystal panel 100 a, a colorfilter CF is formed between the second glass substrate 2 and the counterelectrode 21. A polarizing plate 29 is bonded to the other surface ofthe second glass substrate 2. In the polarizing plate 19 and thepolarizing plate 29, polarization directions (polarization planes) oflight beams passing therethrough are different by 90°. A backlight (notillustrated) is provided on the other surface side (side on which thepolarizing plate 19 is bonded) of the first glass substrate 1.

In the configuration described above, for example, in the case of anormally black mode, when no voltage is applied between each of thesubpixel electrodes 11 a and 11 b and the counter electrode 21 of thepixel P, the polarization direction of light transmitted through thepixel P does not change. Therefore, light emitted from the backlight andtransmitted through the polarizing plate 19 is absorbed by thepolarizing plate 29. In contrast, when a voltage is applied between eachof the subpixel electrodes 11 a and 11 b and the counter electrode 21 ofthe pixel P, the polarization direction of light transmitted through thepixel P changes according to the magnitude of the voltage. Therefore,the light transmitted through the pixel P is transmitted through thepolarizing plate 29 in a state in which the polarization direction oflight emitted from the backlight and transmitted through the polarizingplate 19 changes according to the magnitude of the voltage. As a result,the brightness of an image displayed by the pixel P changes.

Next, the parasitic capacitance not explicitly illustrated in FIG. 2will be described.

FIG. 4 is an explanatory diagram illustrating the parasitic capacitanceassociated with the pixel P. In FIG. 4, for the following description,the pixel P in the k-th line (k is an integer of 0 or more: the samehereinbelow), the scanning signal line Gm of the k-th line, and thedischarge signal line Gs of the k-th line are denoted by Pk, Gmk, andGsk, respectively. Since the parasitic capacitance is similarlyassociated with any pixel Pk, description will be given herein withoutdistinction.

In the TFTs 15 a and 15 b having drain electrodes connected to thesubpixel electrodes 11 a and 11 b of the subpixels SP1 and SP2, aparasitic capacitance is present between the drain and the gate. Inaddition, a stray capacitance is present between the scanning signalline Gmk connected to the gate electrodes of the TFTs 15 a and 15 b andeach of the subpixel electrodes 11 a and 11 b. Since the parasiticcapacitance and the stray capacitance between the drain and the gate actas parallel capacitances, these capacitances are collectively assumed tobe a parasitic capacitance Cgd.

In the TFT 14 having a drain electrode (or a source electrode) connectedto the subpixel electrode 11 b of the subpixel SP2, a parasiticcapacitance is present between the drain and the gate (or between thesource and the gate). In addition, a stray capacitance is presentbetween the discharge signal line Gsk connected to the gate electrode ofthe TFT 14 and the subpixel electrode 11 b. Since the parasiticcapacitance and the stray capacitance between the drain and the gate (orbetween the source and the gate) act as parallel capacitances, thesecapacitances are collectively referred to as a parasitic capacitanceCgp. On the other hand, a stray capacitance is present between thesubpixel electrode 11 a of the subpixel SP1 and a discharge signal lineGsk-1 (for example, between the subpixel electrode 11 a of the subpixelSP1 of the pixel P1 and a discharge signal line Gs0). This is assumed tobe a parasitic capacitance Csp.

Next, the influence of each of the parasitic capacitances describedabove will be described by taking as an example a case where there is aproblem.

FIG. 5 is a timing chart illustrating temporal changes of a signalapplied to each signal line and the voltage of the subpixel electrode 11a. In seven timing charts illustrated in FIG. 5, all the horizontal axesindicate the same time axis, and the vertical axes indicate, from thetop of the diagram, the signal level of the discharge signal line Gs0 ofthe 0-th line, the signal level of the scanning signal line Gm1 of thefirst line, the signal level of the discharge signal line Gs1 of thefirst line, the signal level of the scanning signal line Gm2 of thesecond line, the signal level of the discharge signal line Gs2 of thesecond line, the voltage level of the subpixel electrode 11 a of thesubpixel SP1 of the pixel P1, and the voltage level of the subpixelelectrode 11 a of the subpixel SP1 of the pixel P2. The signal level isexpressed with an ON state as a positive pulse, and the voltage level isexpressed as a potential difference with respect to the potential of thecounter electrode 21, that is, a counter voltage Vcom. Each periodbetween broken lines is 1 H. The polarity of the data signal written inthe pixel Pk is inverted every frame and every line.

The scanning signal from the scanning signal line Gmk is generated so asto have a signal width longer than the length of, for example, 1 H witha delay of 1 H for each line. When the scanning signal from the scanningsignal line Gm1 (or Gm2) is turned on during a period from time t0 to t1(or from t1 to t2), the TFTs 15 a and 15 b of the pixel P1 (or P2) areturned on (conductive state), and the data signal from the source signalline SL is applied to the subpixel electrodes 11 a and 11 b and theauxiliary capacitor electrodes 12 a and 12 b (refer to FIG. 2) of thepixel P1 (or P2). As a result, the voltages of the subpixel electrodes11 a and 11 b become the same level as the voltage of the source signalline SL until time t2 (or until t3). This voltage is a voltage appliedto the liquid crystal capacitors Clc1 and Clc2. In addition,illustration of the voltage level of the subpixel electrode 11 b will beomitted. The voltage waveform of the subpixel electrode 11 a of thepixel P1 has a waveform similar to that obtained by inverting thepolarity with respect to Vcom after one frame and shifting the voltagewaveform of the subpixel electrode 11 a of the pixel P2 illustrated inFIG. 5 to the left by 1 H.

Thereafter, when the scanning signal from the scanning signal line Gm1(or Gm2) is turned on at time t2 (or t3), the TFTs 15 a and 15 b of thepixel P1 (or P2) is turned off (non-conductive state). At time t2 (ort3), the voltage levels of the subpixel electrodes 11 a and 11 bslightly drop due to the influence of a so-called pull-in phenomenon(feed-through) caused by the parasitic capacitance Cgd. In this case,since the absolute values of the voltage levels of the subpixelelectrodes 11 a and 11 b change depending on whether the polarity withrespect to Vcom is positive or negative, the average voltage of thevoltages applied to the liquid crystal capacitors Clc1 and Clc2 isadjusted to become Vcom after the influence of the pull-in phenomenon.The counter voltage adjusted as described above is referred to as anoptimum counter voltage.

Incidentally, it is necessary to prevent the discharge signal from thedischarge signal line Gs1 (or Gs2) for turning on the TFT 14 of thepixel P1 (or P2) from overlapping the scanning signal from the scanningsignal line Gm1 (or Gm2). Therefore, in FIG. 5, the discharge signallines Gs0, Gs1, and Gs3 are respectively connected to the scanningsignal lines Gm2, Gm3, and Gm4 behind two lines (Gm3 and Gm4 are notillustrated) (refer to FIG. 1), so that the discharge signal is delayedby 2 H from the scanning signal for all lines. When the TFT 14 is turnedon by the discharge signal, the discharge capacitor Cdc illustrated inFIG. 2 is connected in parallel to the liquid crystal capacitor Clc2 andthe auxiliary capacitor Ccs2.

In this case, since the charge accumulated in the discharge capacitorCdc is a charge accumulated before one frame, the charge accumulated inthe discharge capacitor Cdc has a polarity opposite to the polarity ofthe charge accumulated in the liquid crystal capacitor Clc2 and theauxiliary capacitor Ccs2. For this reason, during a period from time t3to t4 (or t4 to t5), a positive charge (or a negative charge) moves fromthe liquid crystal capacitor Clc2 and the auxiliary capacitor Ccs2 tothe discharge capacitor Cdc to reduce the absolute value of the voltageapplied to the liquid crystal capacitor Clc2. On the other hand, sincethe voltage applied to the liquid crystal capacitor Clc1 is notinfluenced by the turning on of the TFT 14, the absolute value of thevoltage applied to the liquid crystal capacitor Clc2 is smaller than theabsolute value of the voltage applied to the liquid crystal capacitorClc1. Therefore, the effect of improving the viewing angle dependence ofthe gamma characteristics is obtained.

Here, focus is given to the influence of the parasitic capacitance Csp,which is present between the subpixel electrode 11 a of the subpixel SP1of the pixel P1 (or P2) and the discharge signal line Gs0 (or Gs1), onthe subpixel electrode 11 a of the subpixel SP1 of the pixel P1 (or P2).The discharge signal from the discharge signal line Gs0 rises earlier by1 H than the rising time of the discharge signal from the dischargesignal line Gs1, and falls at time t3. During at least a period fromtime t1 to t2 (or from t2 to t3) in which the scanning signal from thescanning signal line Gm1 (or Gm2) is ON, the subpixel electrode 11 a isconnected to the source signal line SL by the TFT 15 a and is in a lowimpedance state. Therefore, it is negligible that the voltage of thesubpixel electrode 11 a of the pixel P1 (or P2) is influenced by push-upor push-down from the discharge signal line Gs0 (or Gs1) through theparasitic capacitance Csp.

In contrast, after time t2 (or after t3) at which the scanning signalfrom the scanning signal line Gm1 (or Gm2) is off, the voltage of thesubpixel electrode 11 a of the pixel P1 (or P2) is held by the liquidcrystal capacitor Clc1 and the auxiliary capacitor Ccs1. Accordingly,the voltage tends to fluctuate due to the movement of charge from and tothe outside. Specifically, the voltage level of the subpixel electrode11 a of the pixel P1 (or P2) is hardly influenced by the rise at theleading edge of the discharge signal, while the voltage level of thesubpixel electrode 11 a of the pixel P1 (or P2) is influenced by thetrailing edge of the discharge signal and is pushed down at time t3 (ort4).

Since the above-described push-down occurs in the same directionregardless of whether the voltage of the subpixel electrode 11 a has apositive or negative polarity, a phenomenon (counter voltage deviation)occurs in which the optimum counter voltage for the subpixel electrode11 a of the subpixel SP1 is shifted in a direction in which the optimumcounter voltage becomes lower than the actual counter voltage Vcom. Whenthe counter voltage deviation occurs, a DC voltage is applied to theliquid crystal capacitor Clc1. Accordingly, there is a problem thatso-called burn-in or flicker occurs.

In addition, in the example of the timing chart illustrated in FIG. 5,the subpixel electrode 11 b of the subpixel SP2 of the pixel P1 (or P2)is almost equally influenced by push-up and push-down from the dischargesignal line Gs1 (or Gs2) through the parasitic capacitance Cgp, which ispresent between the subpixel electrode 11 b of the subpixel SP2 of thepixel P1 (or P2) and the discharge signal line Gs1 (or Gs2). Therefore,these influences are canceled out to cause no problem.

In order to avoid the problem occurring in the case of FIG. 5, thedischarge signal may be delayed by 3 H or more from the scanning signalfor all lines, or the signal widths of the scanning signal and thedischarge signal may be made shorter than the length of 1 H so that thedischarge signal from the discharge signal line Gs0 (or Gs1) does notoverlap the scanning signal from the scanning signal line Gm1 (or Gm2).In general, when the signal widths of the scanning signal and thedischarge signal are shorter than the length of 1 H, the dischargesignal line Gs of each line may be connected to the scanning signal lineGm behind two lines that is scanned after 2 H. When the signal widths ofthe scanning signal and the discharge signal are longer than M times (Mis an integer of 0 or more) the length of 1 H and shorter than (M+1)times, the discharge signal line Gs of each line may be connected to thescanning signal line Gm behind (M+2) lines or more.

Hereinafter, a specific example in which the problem of the presentapplication is solved will be described.

FIGS. 6A and 6B are timing charts illustrating temporal changes of asignal applied to each signal line and the voltage of the subpixelelectrode 11 a in the liquid crystal display device according toEmbodiment 1. In seven timing charts illustrated in FIGS. 6A and 6B, allthe horizontal axes indicate the same time axis, and the vertical axesindicate, from the top of the diagram, the signal level of the dischargesignal line Gs0 of the 0-th line, the signal level of the scanningsignal line Gm1 of the first line, the signal level of the dischargesignal line Gs1 of the first line, the signal level of the scanningsignal line Gm2 of the second line, the signal level of the dischargesignal line Gs2 of the second line, the voltage level of the subpixelelectrode 11 a of the subpixel SP1 of the pixel P1, and the voltagelevel of the subpixel electrode 11 a of the subpixel SP1 of the pixelP2. The signal level is expressed with an ON state as a positive pulse,and the voltage level is expressed as a potential difference withrespect to the potential of the counter electrode 21, that is, a countervoltage Vcom. Each period between broken lines is 1 H.

FIG. 6A is different from FIG. 6B in that the signal widths of thescanning signal and the discharge signal are less than the length of 1 Hin FIG. 6A while the signal widths of the scanning signal and thedischarge signal are longer than the length of 1 H and less than thelength of 2 H in FIG. 6B. The point that the scanning signal from thescanning signal line Gmk is delayed by 1 H every line and the point thatthe leading edge (rising edge in FIGS. 6A and 6B) of the dischargesignal from the discharge signal line Gsk-1 is delayed by time(corresponding to a predetermined time) Td or more compared with thetrailing edge (falling edge in FIGS. 6A and 6B) of the scanning signalfrom the scanning signal line Gmk are common in FIGS. 6A and 6B. This isthe same for a case where the signal widths of the scanning signal andthe discharge signal are longer than the length of 2 H.

In the case of FIG. 6A, the discharge signal lines Gs0, Gs1, and Gs3 arerespectively connected to the scanning signal lines Gm2, Gm3, and Gm4behind two lines, so that the discharge signal is delayed by 2 H fromthe scanning signal for all lines. In a case where the scanning signalfrom the scanning signal line Gm1 (or Gm2) rises during a period fromtime t1 to t2 (or from time t2 to t3) to turn on the TFTs 15 a and 15 band then falls at time t2 (or t3), the voltage level of the subpixelelectrode 11 a slightly decreases due to the influence of the pull-inphenomenon (feed-through). Thereafter, the discharge signal from thedischarge signal line Gs0 (or Gs1) rises with a delay of Td or more, andthe discharge signal falls at time t3 (or t4). During this period, thevoltage level of the subpixel electrode 11 a of the pixel P1 (or P2) isalmost equally influenced by push-up and push-down due to the rising andfalling of the discharge signal from the discharge signal line Gs0 (orGs1). Therefore, the voltage level of the subpixel electrode 11 a of thepixel P1 (or P2) is maintained at almost the same voltage as when thereis no influence of these discharge signals.

When the case of FIG. 5 is compared with the case of FIG. 6A, the signalwidths of the scanning signal and the discharge signal are shorter thanthe length of 1 H in the case of FIG. 6A. Therefore, the same effect aswhen the discharge signal of each line is delayed by 3 H from thescanning signal in the case of FIG. 5 in which these signal widths arelonger than the length of 1 H is obtained. As will be described inEmbodiment 2 to be described later, it is preferable to secure about 2μs as the length of Td. However, even if the length of Td is 2 μs orless, the effect of the present invention is not lost.

On the other hand, in the case of FIG. 6B, the discharge signal linesGs0, Gs1, and Gs3 are respectively connected to the scanning signallines Gm2, Gm3, and Gm4 behind three lines, so that the discharge signalis delayed by 3 H from the scanning signal for all lines. In a casewhere the scanning signal from the scanning signal line Gm1 (or Gm2)rises during a period from time t0 to t1 (or from time t1 to t2) to turnon the TFTs 15 a and 15 b and then falls at time t2 (or t3), the voltagelevel of the subpixel electrode 11 a slightly decreases due to theinfluence of the pull-in phenomenon (feed-through). Thereafter, thedischarge signal from the discharge signal line Gs0 (or Gs1) rises witha delay of Td or more, and the discharge signal falls at time t4 (ort5). During this period, the voltage level of the subpixel electrode 11a of the pixel P1 (or P2) is almost equally influenced by push-up andpush-down due to the rising and falling of the discharge signal from thedischarge signal line Gs0 (or Gs1). Therefore, the voltage level of thesubpixel electrode 11 a of the pixel P1 (or P2) is maintained at almostthe same voltage as when there is no influence of these dischargesignals.

When the case of FIG. 5 is compared with the case of FIG. 6B, the pointthat the signal widths of the scanning signal and the discharge signalare longer than the length of 1 H and shorter than the length of 2 H iscommon. However, in the case of FIG. 6B, the delay of the dischargesignal with respect to the scanning signal of each line is increased by1 H as compared with the case of FIG. 5. Therefore, there is an effectof preventing the counter voltage deviation by suppressing the delay ofthe discharge signal to the minimum.

As described above, according to the present Embodiment 1, each of thepixels P arranged in a matrix has at least the first subpixel SP1 andthe second subpixel SP2 defined to include an electrode pair of each ofthe subpixel electrodes 11 a and 11 b and the counter electrode 21,which face each other with the liquid crystal layer 3 interposedtherebetween, and the scanning signal from the scanning signal line Gmof each row (that is, each line) of the matrix is applied to the gateelectrodes of the TFTs 15 a and 15 b for applying the data signal to thesubpixel electrodes 11 a and 11 b respectively included in the firstsubpixel SP1 and the second subpixel SP2. The discharge capacitorelectrode 13 is connected to the subpixel electrode 11 b of the secondsubpixel SP2 through the TFT 14, and the discharge capacitor counterelectrode 23 connected to the potential of the counter electrode 21faces the discharge capacitor electrode 13. The signal width of thescanning signal is within a range from M times (M is 0 or 1) the lengthof 1 H to (M+1) times, and the discharge signal line Gs for applying thedischarge signal to each line is connected to the scanning signal lineGm behind N lines, which is scanned after N horizontal scanning periods(N is M+2, that is, 2 or 3), by the signal-to-signal connection lineWsm.

Therefore, after a point in time at which no data signal is applied tothe subpixel electrodes 11 a and 11 b of the first subpixel SP1 and thesecond subpixel SP2 of each line, the discharge signal is applied to thegate electrode of the TFT 14 of the previous line. As a result, for thevoltage applied to the liquid crystal layer 3 by the first subpixel SP1and the second subpixel SP2 that the pixel P of each line has at least,influences of the rising and falling of the discharge signal of theprevious line are canceled out.

Therefore, it is possible to prevent the counter voltage, which isoptimal for the counter electrode 21 that the subpixel electrodes 11 aand 11 b defining the pixel P face, from deviating from the presetcounter voltage.

In addition, according to Embodiment 1, the arrangement direction of thefirst subpixel SP1 and the second subpixel SP2 is a direction crossingthe discharge signal line Gs, that is, the row direction, the dischargesignal line Gs is arranged between the subpixel SP1 and the subpixel SP2adjacent to each other in the pixels P and P adjacent to each other inthe row direction, and the scanning signal line is arranged between thesubpixel SP1 and the subpixel SP2 in the pixel P.

Therefore, leakage of a signal between the discharge signal line Gs andthe scanning signal line Gm can be suppressed. As a result, themanufacturing yield of the liquid crystal panel 100 a is improved. Onthe other hand, due to the configuration described above, the parasiticcapacitance Csp between the discharge signal line Gs and the firstsubpixel SP1 increases. In such a case, however, there is an effect ofpreventing the counter voltage deviation.

In addition, according to Embodiment 1, the polarity of the data signalapplied to each pixel P is inverted every frame. Therefore, the voltageof the subpixel electrode 11 b of the second subpixel SP2 is effectivelychanged when the TFT 14 is turned on, so that it is possible to increasethe contrast difference between the two subpixels.

In addition, according to Embodiment 1, an electrode pair defining eachof the first subpixel SP1 and the second subpixel SP2 that the pixel Phave includes an electrode pair of the auxiliary capacitor electrode 12a and the auxiliary capacitor counter electrode 22 a and an electrodepair of the auxiliary capacitor electrode 12 b and the auxiliarycapacitor counter electrode 22 b. The auxiliary capacitor electrodes 12a and 12 b are electrically connected to the subpixel electrodes 11 aand 11 b, respectively, and each of the auxiliary capacitor counterelectrodes 22 a and 22 b is connected to the potential of the counterelectrode 21 that is the connection destination of the dischargecapacitor counter electrode 23.

Therefore, since the auxiliary capacitor Ccs1 formed by the auxiliarycapacitor electrode 12 a and the auxiliary capacitor counter electrode22 a and the auxiliary capacitor Ccs2 formed by the auxiliary capacitorelectrode 12 b and the auxiliary capacitor counter electrode 22 b arerespectively connected in parallel to the liquid crystal capacitors Clc1and Clc2 formed by the subpixel electrodes 11 a and 11 b and the counterelectrode 21 of the first subpixel SP1 and the second subpixel SP2, itis possible to stably hold the voltage applied to the liquid crystallayer 3 by the first subpixel SP1 and the second subpixel SP2 for atleast one frame period. Thus, with the configuration in which theoptimum counter voltage can be stably set, it is possible to make theeffect of preventing the counter voltage deviation to the utmost.

In addition, according to Embodiment 1, the scanning signal line Gm andthe signal-to-signal connection line Wsm are wired in the edge portion101 a on one side of the liquid crystal panel 100 a, and thesignal-to-signal connection line Wsm intersects with the (N−1) (=1)scanning signal lines Gm at the edge portion 101 a.

That is, the signal-to-signal connection line Wsm connects the dischargesignal line Gs and the scanning signal line Gm behind N lines, which isscanned after N(=2) horizontal scanning periods, to each other in aone-to-one manner, and the scanning signal is applied to each scanningsignal line Gm from the edge portion 101 a side on which thesignal-to-signal connection line Wsm is wired. Accordingly, thesignal-to-signal connection line Wsm and the (N−1) scanning signal linesGm inevitably intersect with each other at the edge portion 101 a on oneside of the liquid crystal panel 100 a.

Modification Example 1

The signal widths of the scanning signal and the discharge signal areset to lengths different from the length of 1 H in Embodiment 1, whereasthe signal widths of the scanning signal and the discharge signal areset to the length of approximately 1 H in Modification Example 1 ofEmbodiment 1. In the present Modification Example 1, when the effect ofthe present invention is reduced because Td illustrated in FIGS. 6A and6B of Embodiment 1 is shorter than a predetermined time, an effectivesolution is presented.

FIG. 7 is an explanatory diagram illustrating a connection example ofthe signal-to-signal connection line Wsm in the liquid crystal panelaccording to Modification Example 1 of Embodiment 1, and FIG. 8 is atiming chart illustrating temporal changes of the scanning signal andthe discharge signal in the liquid crystal panel according toModification Example 1 of Embodiment 1. Since the liquid crystal panelin the present Modification Example 1 is different from the liquidcrystal panel 100 a of Embodiment 1 only in the connection destinationof the signal-to-signal connection line Wsm, illustration thereof willbe omitted. Hereinafter, the same configurations as in Embodiment 1 aredenoted by the same reference numerals and the description thereof willbe omitted, and a configuration different from Embodiment 1 will bedescribed.

In FIG. 7, for the sake of explanation, the pixel P of the n-th line (nis a natural number), the scanning signal line Gm of the n-th line, andthe discharge signal line Gs of the n-th line are denoted by Pn, Gm_n,and Gs_n, respectively. In addition, the reference numerals of thesubpixels SP1 and SP2 and the reference numerals of the TFTs 15 a, 15 b,and 14 are displayed only for the pixel Pn of the n-th line among thepixels Pn, Pn+1, . . . , Pn+5. The TFTs 15 a, 15 b, and 14 are expressedby ellipses filled with black for simplicity. The discharge signal linesGs_n, Gs_n+1, and Gs_n+2 are separately connected to the scanning signallines Gm_n+3, Gm_n+4, and Gm_n+5 behind three lines, which are scannedafter three horizontal scanning periods, by the signal-to-signalconnection line Wsm. This is the same for the discharge signal linesGs_n+3, Gs_n+4, and Gs_n+5 whose connection destinations are notillustrated.

Returning to FIG. 8, in seven timing charts illustrated in the diagram,all the horizontal axes indicate the same time axis, and the verticalaxes indicate, from the top of the diagram, the signal levels of thescanning signal line Gm_n and the discharge signal line Gs_n of the n-thline, the signal levels of the scanning signal line Gm_n+1 and thedischarge signal line Gs_n+1 of the (n+1)-th line, the signal levels ofthe scanning signal line Gm_n+2 and the discharge signal line Gs_n+2 ofthe (n+2)-th line, and the signal level of the scanning signal lineGm_n+3 of the (n+3)-th line. The signal level is expressed with an ONstate as a positive pulse. Each period between broken lines is 1 H. Thesignal widths of the scanning signal and the discharge signal are eachapproximately 1 H in length. The scanning signal is generated so as tobe delayed by 1 H every line.

Due to the connection illustrated in FIG. 7, in FIG. 8, the dischargesignal is delayed by 3 H from the scanning signal for all lines. In acase where the scanning signal from the scanning signal line Gm_n+1 (orGm_n+2 or Gm_n+3) rises at time t1 (or time t2 or t3) to turn on theTFTs 15 a and 15 b and then falls at time t2 (or t3 or t4), the voltagelevel of the subpixel electrode 11 a slightly decreases due to theinfluence of the pull-in phenomenon (feed-through).

Thereafter, the discharge signal from the discharge signal line Gs_n (orGs_n+1 or Gs_n+2) rises with a delay of 1 H, and the discharge signalfalls at time t4 (or t5 or t6). During this period, for example, thevoltage level of the subpixel electrode 11 a of the pixel Pn+1 (or Pn+2or Pn+3) is almost equally influenced by push-up and push-down due tothe rising and falling of the discharge signal from the discharge signalline Gs_n (or Gs_n+1 or Gs_n+2). Therefore, since the voltage level ofthe subpixel electrode 11 a of the pixel Pn+1 (or Pn+2 or Pn+3) ismaintained at almost the same voltage as when there is no influence ofthese discharge signals, the counter voltage deviation is prevented.

In general, when the signal widths of the scanning signal and thedischarge signal are longer than a length, which is obtained bysubtracting a predetermined time (for example, 2 μs described above)from the length of 1 H, and shorter than the length of 1 H, thedischarge signal line Gs of each line may be connected to the scanningsignal line Gm behind three lines that is scanned after 3 H. When thesignal widths of the scanning signal and the discharge signal are longerthan a length, which is obtained by subtracting a predetermined timefrom (M+1) times (M is an integer of 0 or more) the length of 1 H, andshorter than (M+1) times the length of 1 H, the discharge signal line Gsof each line may be connected to the scanning signal line Gm behind(M+3) lines or more.

In addition, the configuration of the present Modification Example 1 isdifferent from the configuration of Embodiment 1 in that theconfiguration of the present Modification Example 1 can be applied toother Modification Examples and other embodiments to be described later.

As described above, according to the present Modification Example 1, thesignal widths of the scanning signal and the discharge signal are longerthan a length, which is obtained by subtracting a predetermined time Tdfrom (M+1) times (M is an integer of 0 or more) the length of 1 H, andshorter than (M+1) times the length of 1 H, and the discharge signalline Gs is connected to the scanning signal line Gm of a row, which isscanned after L horizontal scanning periods (L is M+3 or more, that is,3 or more), by the signal-to-signal connection line Wsm.

Therefore, since the discharge signal line Gs is connected to thescanning signal line Gm behind L lines, which is scanned after Lhorizontal scanning periods (L is an integer larger by 1 than the aboveN), it is possible to avoid the application of the discharge signal tothe gate electrode of the TFT 14 of the previous line within apredetermined time from the point in time at which no data signal isapplied to the subpixel electrodes 11 a and 11 b of the first subpixelSP1 and the second subpixel SP2 of each line. As a result, the countervoltage deviation is prevented.

Modification Example 2

The auxiliary capacitor counter electrodes 22 a and 22 b and thedischarge capacitor counter electrode 23 are connected to the potentialof the counter electrode 21 in Embodiment 1, whereas the auxiliarycapacitor counter electrodes 22 a and 22 b and the discharge capacitorcounter electrode 23 are connected to a predetermined potentialdifferent from the potential of the counter electrode 21 in ModificationExample 2 of Embodiment 1.

FIG. 9 is a block diagram illustrating an example of the configurationof a liquid crystal display device according to Modification Example 2of Embodiment 1, and FIG. 10 is an explanatory diagram schematicallyillustrating a configuration for defining the pixel P in the liquidcrystal display device according to Modification Example 2 ofEmbodiment 1. The liquid crystal display device according to the presentModification Example 2 includes a liquid crystal panel 100 b, a gatedriver GDa, a source driver SDa, a display control circuit 4 b forcontrolling the display of the liquid crystal panel 100 b using the gatedriver GDa and the source driver SDa, and an auxiliary capacitor voltagemain wiring CSL for relaying a voltage applied from the display controlcircuit 4 b to the liquid crystal panel 100 b. Hereinafter, the sameconfigurations as in Embodiment 1 are denoted by the same referencenumerals and the description thereof will be omitted, and aconfiguration different from Embodiment 1 will be described.

Compared with the liquid crystal panel 100 a of Embodiment 1, the liquidcrystal panel 100 b further includes auxiliary capacitor voltage linesCS1 and CS2 arranged so as to linearly cross both end portions of thepixel P, which are located in the vertical direction, in the horizontaldirection. Each of the auxiliary capacitor voltage lines CS1 and CS2 isconnected to the auxiliary capacitor voltage main wiring CSL outside theliquid crystal panel 100 b, and is connected to the auxiliary capacitorcounter electrodes 22 a and 22 b inside the liquid crystal panel 100 b(refer to FIG. 10). The auxiliary capacitor voltage line CS2 is furtherconnected to the discharge capacitor counter electrode 23. Although theauxiliary capacitor voltage line CS2 is connected to the auxiliarycapacitor voltage main wiring CSL outside the liquid crystal panel 100 bin the present Modification Example 2, the auxiliary capacitor voltagemain wiring CSL may be arranged inside the liquid crystal panel 100 b.

In an edge portion 101 b on one side of the liquid crystal panel 100 b,the signal-to-signal connection line Wsm that connects each dischargesignal line Gs and the scanning signal line Gm behind two lines, whichis scanned after two horizontal scanning periods, to each other isseparately wired. In addition, the scanning signal line Gm and theauxiliary capacitor voltage lines CS1 and CS2 extending from the displayregion are wired in the edge portion 101 b. The signal-to-signalconnection line Wsm intersects with one scanning signal line Gm at theedge portion 101 b in the same manner as in the case of Embodiment 1.

Compared with the display control circuit 4 a in Embodiment 1, thedisplay control circuit 4 b further includes an auxiliary capacitorvoltage generation circuit 44 for generating a predetermined voltage tobe applied to the auxiliary capacitor voltage lines CS1 and CS2 throughthe auxiliary capacitor voltage main wiring CSL. The voltages applied tothe auxiliary capacitor voltage lines CS1 and CS2 may be the same ordifferent.

The liquid crystal panel 100 a and the liquid crystal panel 100 b aredifferent according to whether the connection destination of each of theauxiliary capacitor counter electrodes 22 a and 22 b and the dischargecapacitor counter electrode 23 is the potential of the counter electrode21 or the potential of the auxiliary capacitor voltage lines CS1 andCS2. However, it is obvious that there is no difference for the effectthat the auxiliary capacitors Ccs1 and Ccs2 are respectively connectedin parallel to the liquid crystal capacitors Clc1 and Clc2 to storecharges and the amount of positive charges (or negative charges) thatmove from the liquid crystal capacitor Clc2 and the auxiliary capacitorCcs2 to the discharge capacitor Cdc when the TFT 14 is turned on. Fromthis fact, according to the present Modification Example 2, it can besaid that completely the same effect as in Embodiment 1 is obtained.

In addition, the difference between the configuration of Embodiment 1and the configuration of the present Modification Example 2 can beapplied to Modification Example 1 described above and ModificationExample 3 and other embodiments to be described later.

Modification Example 3

The absolute value of the effective voltage that is applied to theliquid crystal capacitor Clc1 when the TFT 14 is turned on does notchange in Embodiment 1, whereas the absolute value of the effectivevoltage that is applied to the liquid crystal capacitor Clc1 when theTFT 14 is turned on changes in Modification Example 3 of Embodiment 1.

FIG. 11 is an explanatory diagram schematically illustrating aconfiguration for defining the pixel P in a liquid crystal panelaccording to Modification Example 3 of Embodiment 1.

In the present Modification Example 3, a second discharge capacitor(capacitor) Cdc2 formed by an electrode pair having electrodesrespectively connected to the discharge capacitor electrode 13 and theauxiliary capacitor electrode 12 a is connected to the configuration ofthe pixel P in Embodiment 1. The difference between the liquid crystalpanel in the present Modification Example 3 and the liquid crystal panel100 a in Embodiment 1 is only the presence or absence of the dischargecapacitor Cdc2. In addition, portions corresponding to Embodiment 1 aredenoted by the same reference numerals, and the description thereof willbe omitted.

Hereinafter, a change in a voltage that is applied to the subpixelelectrodes 11 a and 11 b when the TFT 14 is turned on will be described.

In the description of Embodiment 1, when the TFT 14 is turned on, apositive charge (or a negative charge) moves from the liquid crystalcapacitor Clc2 and the auxiliary capacitor Ccs2 to the dischargecapacitor Cdc and the absolute value of the voltage applied to theliquid crystal capacitor Clc2 is reduced while the absolute value of thevoltage applied to the liquid crystal capacitor Clc1 does not change. Inaddition, the voltage of the discharge capacitor electrode 13immediately before the TFT 14 is turned on is the voltage of thesubpixel electrode 11 b before one frame. On the other hand, in thepresent Modification Example 3, due to the presence of the seconddischarge capacitor Cdc2, the voltage of the discharge capacitorelectrode 13 immediately before the TFT 14 is turned on is differentfrom the voltage of the subpixel electrode 11 b before one frame. Forthis reason, when the TFT 14 is turned on, there is a difference thatthe absolute value of the voltage applied to the liquid crystalcapacitor Clc1 also changes.

In order to describe this specifically, the electrostatic capacitancesof the liquid crystal capacitors Clc1 and Clc2, the auxiliary capacitorsCcs1 and Ccs2, and the discharge capacitor Cdc and the second dischargecapacitor Cdc2 are denoted by CLC, CCS, and CDC, and CDC2, respectively.Referring to the timing chart illustrated in FIG. 6A, the voltages ofthe subpixel electrodes 11 a and 11 b of the pixel P1 at time t1 beforethe TFTs 15 a and 15 b are turned on by the scanning signal from thescanning signal line Gm1 and the data signal is applied are denoted byV1 and V2, respectively. In addition, the voltage of each of thesubpixel electrodes 11 a and 11 b of the pixel P1 at time t2 when thedata signal is applied is denoted by V3. The polarity of the voltage V3is opposite to the polarities of the voltages V1 and V2. The voltage ofthe discharge capacitor electrode 13 at time t1 is maintained at thesame voltage V2 as the voltage of the subpixel electrode 11 b from whenthe TFT 14 is turned on/off before one frame.

Due to the application of the data signal to the subpixel electrode 11 aof the pixel P1, the voltage of the subpixel electrode 11 a rises (ordrops) from V1 to V3. This change in voltage V3-V1 is divided by theseries circuit of the second discharge capacitor Cdc2 and the dischargecapacitor Cdc and is added to the voltage of the discharge capacitorelectrode 13. Accordingly, the voltage Vdc of the discharge capacitorelectrode 13 at time t2 is expressed by the following Equation (1).

Vdc=V2+(V3−V1)×CDC2/(CDC+CDC2)  (1)

On the right side of Equation (1), the polarities of V2 of the firstterm and (V3−V1) of the second term are opposite. In order for apositive charge (or a negative charge) to move from the liquid crystalcapacitor Clc2 and the auxiliary capacitor Ccs2 to the dischargecapacitor Cdc side when the TFT 14 is turned on later, it is preferablethat the polarity of Vdc is opposite to the polarity of V3 (that is, thepolarity of Vdc is the same as the polarity of V2). The magnitude ofCDC2/(CDC+CDC2) is appropriately reduced so that such a polarityrelationship is satisfied. In addition, the voltage Vdc is a voltage ofa parallel circuit formed by connecting a series circuit, which isformed by connecting the second discharge capacitor Cdc2 in series to acircuit in which the liquid crystal capacitor Clc1 and the auxiliarycapacitor Ccs1 are connected in parallel to each other, in parallel tothe discharge capacitor Cdc.

Then, it is assumed that, when the TFT 14 is turned on by the dischargesignal from the discharge signal line Gs1 during a period from time t3to t4, a positive charge (or a negative charge) moves from the liquidcrystal capacitor Clc2 and the auxiliary capacitor Ccs2 to theabove-described parallel circuit and Vdc rises (or drops) by ΔV. In thiscase, since ΔV is divided by the above-described series circuit andadded to the voltage (that is, the voltage of the subpixel electrode 11b of the pixel P1) V3 of the liquid crystal capacitor Clc1 and theauxiliary capacitor Ccs1, a voltage V4 of the subpixel electrode 11 a attime t4 rises (or drops) from the voltage V3 as expressed by thefollowing Equation (2).

V4=V3+ΔV×CDC2/(CLC+CCS+CDC2)  (2)

On the other hand, since the voltage of the subpixel electrode 11 bafter a positive charge (or a negative charge) moves from the liquidcrystal capacitor Clc2 and the auxiliary capacitor Ccs2 to theabove-described parallel circuit surely drops (or rises), voltagechanges occurring in the subpixel electrodes 11 a and 11 b due to theturning on of the TFT 14 become different to cause opposite polarities.As a result, since the absolute value of the voltage applied to theliquid crystal capacitor Clc2 is smaller than the absolute value of thevoltage applied to the liquid crystal capacitor Clc1, the effect ofimproving the viewing angle dependence of the gamma characteristics isobtained.

In addition, the timings showing the temporal changes of a signalapplied to each signal line and the voltage of the subpixel electrode 11a in the present Modification Example 3 are the same as thoseillustrated in FIGS. 6A and 6B of Embodiment 1.

In addition, the difference between the configuration of Embodiment 1and the configuration of the present Modification Example 3 can beapplied to Modification Example 1 and Modification Example 2 describedabove and other embodiments to be described later.

As described above, according to the present Modification Example 3,when the TFT 14 is turned on, a part of charges accumulated in thesecond subpixel SP2 move to the first subpixel SP1 through the seconddischarge capacitor Cdc2 formed by an electrode pair having electrodesrespectively connected to the discharge capacitor electrode 13 and thesubpixel electrode 11 a of the first subpixel SP1.

Therefore, it is possible to change the voltages of the subpixelelectrode 11 a of the first subpixel SP1 and the subpixel electrode 11 bof the second subpixel SP2 so as to have opposite polarities. Asdescribed above, even in the configuration in which the voltages of thesubpixel electrodes 11 a and 11 b are changed so as to have oppositepolarities when the discharge signal is turned on, the effect ofpreventing the counter voltage deviation is not adversely affected.

Embodiment 2

The same data signal for each line is applied from the source signalline SL, which is arranged for each column of the matrix, to thesubpixel electrodes 11 a and 11 b through the TFTs 15 a and 15 b inEmbodiment 1, whereas data signals that are different alternately forrespective lines are applied from two source signal lines SL1 and SL2,which are arranged for each column of the matrix, to the subpixelelectrodes 11 a and 11 b through the TFTs 15 a and 15 b in Embodiment 2.

FIG. 12 is a block diagram illustrating an example of the configurationof a liquid crystal display device according to Embodiment 2 of thepresent invention. The liquid crystal display device according to thepresent Embodiment 2 includes a liquid crystal panel 100 c, a gatedriver GDb, a source driver SDb, and a display control circuit 4 c forcontrolling the display of the liquid crystal panel 100 c using the gatedriver GDb and the source driver SDb. Hereinafter, the sameconfigurations as in Embodiment 1 are denoted by the same referencenumerals and the majority of the description thereof will be omitted,and a configuration different from Embodiment 1 will be mainlydescribed.

Compared with the liquid crystal panel 100 a of Embodiment 1, the liquidcrystal panel 100 c further includes the source signal line SL1 arrangedin the vertical direction on one side of the pixel P and the sourcesignal line SL2 arranged in the vertical direction on the other side ofthe pixel P. In an edge portion 101 c on one side of the liquid crystalpanel 100 c, the signal-to-signal connection line Wsm that connects eachdischarge signal line Gs and the scanning signal line Gm behind fourlines, which is scanned after two horizontal scanning periods, to eachother is separately wired. The signal-to-signal connection line Wsmintersects with three scanning signal lines Gm at the edge portion 101c.

The display control circuit 4 c is different from the display controlcircuit 4 a in Embodiment 1 in that a source signal control circuit 41 bcontrols the two source signal lines SL1 and SL2 for each column of thematrix using the source driver SDb and a scanning signal control circuit42 b simultaneously controls the scanning signal lines Gm and Gm of twoadjacent rows using the gate driver GDb.

FIG. 13 is an explanatory diagram illustrating the connectionrelationship between the pixel P and the source signal line SL1 or SL2.Since the parasitic capacitance associated with the pixel P is the sameas that illustrated in FIG. 4 of Embodiment 1, the description thereofwill be omitted. Source electrodes of the TFTs 15 a and 15 b of thepixels P1, P3, P5, . . . are connected to the source signal line SL1.Source electrodes of the TFTs 15 a and 15 b of the pixels P2, P4, P6, .. . are connected to the source signal line SL2. That is, data signalsthat are different alternately for respective lines are applied from thesource signal lines SL1 and SL2 to the subpixel electrodes 11 a and 11 bthrough the TFTs 15 a and 15 b. With this configuration, bysimultaneously turning on the scanning signals from the scanning signallines Gm1 and Gm2, it is possible to simultaneously scan two linesincluding the pixels P1 and P2 within 1 H (horizontal scanning period).

In the present Embodiment 2, the discharge signals from the dischargesignal lines Gs1 and Gs2 are simultaneously turned on, but it is thesame as in Embodiment 1 that it is necessary to prevent these dischargesignals from overlapping the scanning signals from the scanning signallines Gm1 and Gm2. As long as this condition is cleared with margin, thesubpixel electrode 11 b of the subpixel SP2 of each of the pixels P1 andP2 is almost equally influenced by push-up and push-down from thedischarge signal lines Gs1 and Gs2 through the parasitic capacitanceCgp, which is present between the subpixel electrode 11 b of thesubpixel SP2 of each of the pixels P1 and P2 and each of the dischargesignal lines Gs1 and Gs2. Therefore, basically no counter voltagedeviation occurs for the second subpixel SP2 of each of the pixels P1and P2.

On the other hand, for the first subpixel SP1 of the pixel P1, there isa possibility that the counter voltage deviation occurs in theconfigurations of the inventions disclosed in Non-Patent Document 1 andU.S. Pat. No. 8,952,877. In particular, in the case of scanning twolines simultaneously as in the present Embodiment 2, the scanningsignals are the same, but the discharge signals affected by the firstsubpixel SP1 are different between the first line and the second line.Therefore, the counter voltage deviation is likely to occur remarkablyin the first subpixel SP1 of the first line. As a result, whitehorizontal streaks are visible every two lines on the display screen.

Hereinafter, a specific example in which the problem of the presentapplication is solved will be described.

FIGS. 14A and 14B are timing charts illustrating temporal changes of asignal applied to each signal line and the voltage of the subpixelelectrode 11 a in the liquid crystal display device according toEmbodiment 2. In seven timing charts illustrated in FIGS. 14A and 14B,all the horizontal axes indicate the same time axis, and the verticalaxes indicate, from the top of the diagram, the signal level of thedischarge signal line Gs0 of the 0-th line, the signal level of thescanning signal line Gm1 of the first line, the signal level of thedischarge signal line Gs1 of the first line, the signal level of thescanning signal line Gm2 of the second line, the signal level of thedischarge signal line Gs2 of the second line, the voltage level of thesubpixel electrode 11 a of the subpixel SP1 of the pixel P1, and thevoltage level of the subpixel electrode 11 a of the subpixel SP1 of thepixel P2. The signal level is expressed with an ON state as a positivepulse, and the voltage level is expressed as a potential difference withrespect to the potential of the counter electrode 21, that is, a countervoltage Vcom. Each period between broken lines is 1 H.

FIG. 14A is different from FIG. 14B in that the signal widths of thescanning signal and the discharge signal are less than the length of 1 Hin FIG. 14A while the signal widths of the scanning signal and thedischarge signal are longer than the length of 1 H and less than thelength of 2 H in FIG. 14B. The point that the scanning signal from thescanning signal line Gmk (k is an integer of 0 or more) is turned onsimultaneously in two lines, the point that the scanning signal and thedischarge signal are turned on with a delay of 1 H every two lines, andthe point that the leading edge (rising edge in FIGS. 14A and 14B) ofthe discharge signal from the discharge signal line Gsk-1 is delayed byTd or more compared with the trailing edge (falling edge in FIGS. 14Aand 14B) of the scanning signal from the scanning signal line Gmk arecommon in FIGS. 14A and 14B. This is the same for a case where thesignal widths of the scanning signal and the discharge signal are longerthan the length of 2 H.

In FIG. 14A, in a case where the scanning signals from the scanningsignal lines Gm1 and Gm2 rise during a period from time t1 to t2 to turnon the TFTs 15 a and 15 b and then falls at time t2, the voltage levelof the subpixel electrode 11 a slightly decreases due to the influenceof the pull-in phenomenon (feed-through). Thereafter, the dischargesignal from the discharge signal line Gs0 (or Gs1) rises with a delay ofTd or more, and the discharge signal falls at time t3 (or t4). Duringthis period, the voltage level of the subpixel electrode 11 a of thepixel P1 (or P2) is almost equally influenced by push-up and push-downdue to the rising and falling of the discharge signal from the dischargesignal line Gs0 (or Gs1). Therefore, the voltage level of the subpixelelectrode 11 a of the pixel P1 (or P2) is maintained at almost the samevoltage as when there is no influence of these discharge signals.

Similarly in FIG. 14B, in a case where the scanning signals from thescanning signal lines Gm1 and Gm2 rise during a period from time t0 tot1 to turn on the TFTs 15 a and 15 b and then falls at time t2, thevoltage level of the subpixel electrode 11 a slightly decreases due tothe influence of the pull-in phenomenon (feed-through). Thereafter, thedischarge signal from the discharge signal line Gs0 (or Gs1) rises witha delay of Td or more, and the discharge signal falls at time t4 (ort5). During this period, the voltage level of the subpixel electrode 11a of the pixel P1 (or P2) is almost equally influenced by push-up andpush-down due to the rising and falling of the discharge signal from thedischarge signal line Gs0 (or Gs1). Therefore, the voltage level of thesubpixel electrode 11 a of the pixel P1 (or P2) is maintained at almostthe same voltage as when there is no influence of these dischargesignals.

Hereinafter, the result of measuring the counter voltage deviation whenthe Td is changed and the visual effect of the present invention will bedescribed.

FIG. 15 is a graph showing the relationship between the delay time ofthe discharge signal and the optimum counter voltage, and FIG. 16 is anexplanatory diagram for describing the presence or absence of horizontalstreaks caused by the counter voltage deviation. In FIG. 15, thehorizontal axis indicates the delay time (μs) of the leading edge of thedischarge signal before one line with respect to the trailing edge ofthe scanning signal, and the vertical axis indicates the optimum countervoltage (V). Here, the liquid crystal display device used for themeasurement is a full HD with a frame rate of 120 Hz, and themeasurement was performed for a case where the displayed gray scale was64/255. The solid line indicates an optimum counter voltage for thesubpixel SP1 of the pixel P1, and the broken line indicates an optimumcounter voltage for the subpixel SP1 of the pixel P2 shown forcomparison. In addition, a case where the value of Td is negativeindicates that the rising edge of the discharge signal of the pixel P0precedes the falling edge of the scanning signal of the pixel P1 intime.

In the present Embodiment 2, the discharge signal for the pixel P0 riseswith a delay of Td or more from the falling edge of the scanning signalfor the pixel P1, and the discharge signal for the pixel P1 rises with adelay of 1 H+Td or more from the falling edge of the scanning signal forthe pixel P2. For this reason, basically no counter voltage deviationoccurs for the subpixel electrode 11 a of the subpixel SP1 of the pixelP2, and the optimum counter voltage is fixed at approximately 6.4 V(refer to the broken line in FIG. 15).

On the other hand, for the subpixel electrode 11 a of the subpixel SP1of the pixel P1, when Td is changed to −7.4 μs, −3.0 μs, −0.74 μs, ±0μs, and +1.5 μs, the optimum counter voltage is changed to 5.05 V, 5.12V, 5.60 V, 6.17 V, and 6.42 V. That is, it can be said that the countervoltage deviation still occurs when Td is 0 μs and the counter voltagedeviation is eliminated when Td of 1.5 μs or more is secured.

In addition, when the value of Td that can prevent the counter voltagedeviation differs depending on a position on the display screen, themaximum Td may be adopted.

Returning to FIG. 16, the upper portion of the diagram shows the displayscreen of the liquid crystal panel 100 c when the counter voltagedeviation occurs, and the lower portion shows the display screen of theliquid crystal panel 100 c when no counter voltage deviation occurs.Since the brightness change of the pixel P with respect to the gradationchange is nonlinear, it is known that the brightness of the pixel Ptends to shift toward the brighter side than the ideal brightness whenthe counter voltage deviation occurs. For this reason, when a uniformhalftone screen is displayed, white horizontal streaks are visible everytwo lines on the display screen (refer to the upper diagram). On theother hand, when no counter voltage deviation occurs, white horizontalstreaks are not visible on the display screen (refer to the lowerdiagram).

As described above, according to the present Embodiment 2, the signalwidth of the scanning signal is within a range from M times (M is 0or 1) the length of 1 H to (M+1) times, and the discharge signal line Gsfor applying the discharge signal to each line is connected to thescanning signal line Gm behind 2N lines, which is scanned after Nhorizontal scanning periods (N is M+2, that is, 2 or 3), by thesignal-to-signal connection line Wsm.

Therefore, after a point in time at which no data signal is applied tothe subpixel electrodes 11 a and 11 b of the first subpixel SP1 and thesecond subpixel SP2 of each line, the discharge signal is applied to thegate electrode of the TFT 14 of the previous line. As a result, for thevoltage applied to the liquid crystal layer 3 by the first subpixel SP1and the second subpixel SP2 that the pixel P of each line has at least,influences of the rising and falling of the discharge signal of theprevious line are canceled out.

Therefore, it is possible to prevent the counter voltage, which isoptimal for the counter electrode 21 that the subpixel electrodes 11 aand 11 b defining the pixel P face, from deviating from the presetcounter voltage.

In addition, according to Embodiment 2, data signals that are differentalternately for respective lines are applied from the two source signallines SL1 and SL2, which are arranged for each column of the matrix, tothe subpixel electrode 11 a of the first subpixel SP1 and the subpixelelectrode 11 b of the second subpixel SP2 through the TFTs 15 a and 15b, and the scanning signals of two adjacent lines are simultaneouslyturned on.

Therefore, it is possible to scan two lines within one horizontalscanning period, and it is possible to prevent the counter voltagedeviation even in the configuration in which the counter voltagedeviation is likely to occur in the subpixel SP1 of the pixel P of thefirst line between two lines scanned simultaneously.

Modification Example 4

The signal widths of the scanning signal and the discharge signal areset to lengths different from an integral multiple of the length of 1 Hin Embodiment 1, whereas the signal widths of the scanning signal andthe discharge signal are set to the length of approximately 1 H inModification Example 4 of Embodiment 2. In the present ModificationExample 4, when the effect of the present invention is reduced becauseTd illustrated in FIGS. 14A and 14B of Embodiment 2 is shorter than apredetermined time, an effective solution is presented.

FIG. 17 is an explanatory diagram illustrating a connection example ofthe signal-to-signal connection line Wsm in the liquid crystal panelaccording to Modification Example 4 of Embodiment 2, and FIG. 18 is atiming chart illustrating temporal changes of the scanning signal andthe discharge signal in the liquid crystal panel according toModification Example 4 of Embodiment 2. Since the liquid crystal panelin the present Modification Example 4 is different from the liquidcrystal panel 100 c of Embodiment 2 only in the connection destinationof the signal-to-signal connection line Wsm, the same reference numeralsare given and illustration thereof will be omitted. Hereinafter, thesame configurations as in Embodiment 2 are denoted by the same referencenumerals and the description thereof will be omitted, and aconfiguration different from Embodiment 2 will be described.

In FIG. 17, for the sake of explanation, the pixel P of the n-th line (nis a natural number), the scanning signal line Gm of the n-th line, andthe discharge signal line Gs of the n-th line are denoted by Pn, Gm_n,and Gs_n, respectively. In addition, the reference numerals of thesubpixels SP1 and SP2 and the reference numerals of the TFTs 15 a, 15 b,and 14 are displayed only for the pixel Pn of the n-th line and thepixel Pn+1 of the (n+1)-th line among the pixels Pn, Pn+1, . . . , Pn+5.The TFTs 15 a, 15 b, and 14 are expressed by ellipses filled with blackfor simplicity. The discharge signal lines Gs_n and Gs_n+1 areseparately connected to the scanning signal lines Gm_n+6 and Gm_n+7behind six lines, which are scanned after three horizontal scanningperiods, by the signal-to-signal connection line Wsm. This is the samefor the discharge signal lines Gs_n+2, Gs_n+3, . . . , Gs_n+7 whoseconnection destinations are not illustrated. The signal-to-signalconnection line Wsm intersects with five scanning signal lines Gm at theedge portion 101 c of the liquid crystal panel 100 c.

Returning to FIG. 18, in eleven timing charts illustrated in thediagram, all the horizontal axes indicate the same time axis, and thevertical axes indicate, from the top of the diagram, the signal levelsof the scanning signal line Gm_n and the discharge signal line Gs_n ofthe n-th line, the signal levels of the scanning signal line Gm_n+1 andthe discharge signal line Gs_n+1 of the (n+1)-th line, . . . , thesignal levels of the scanning signal line Gm_n+4 and the dischargesignal line Gs_n+4 of the (n+4)-th line, and the signal level of thescanning signal line Gm_n+5 of the (n+5)-th line. The signal level isexpressed with an ON state as a positive pulse. Each period betweenbroken lines is 1 H. The signal widths of the scanning signal and thedischarge signal are each approximately 1 H in length. The scanningsignal is generated so as to be delayed by 1 H every two lines.

Due to the connection illustrated in FIG. 17, in FIG. 18, the dischargesignal is delayed by 3 H from the scanning signal for all lines. In acase where the scanning signals from the scanning signal lines Gm_n andGm_n+1 (or Gm_n+2 and Gm_n+3 or Gm_n+4 and Gm_n+5) rise at time t0 (ortime t1 or t2) to turn on the TFTs 15 a and 15 b and then falls at timet1 (or t2 or t3), the voltage level of the subpixel electrode 11 aslightly decreases due to the influence of the pull-in phenomenon(feed-through).

Thereafter, the discharge signals from the discharge signal lines Gs_nand Gs_n+1 (or Gs_n+2 and Gs_n+3 or Gs_n+4 and Gs_n+5) rise with a delayof 2 H, and the discharge signals fall at time t4 (or t5 or t6). Duringthis period, for example, the voltage level of the subpixel electrode 11a of each of the pixels Pn+2 and Pn+3 (or Pn+4 and Pn+5) is almostequally influenced by push-up and push-down due to the rising andfalling of the discharge signals from the discharge signal lines Gs_n+1and Gs_n+2 (or Gs_n+3 and Gs_n+4). Therefore, since the voltage level ofthe subpixel electrode 11 a of each of the pixels Pn+2 and Pn+3 (or Pn+4and Pn+5) is maintained at almost the same voltage as when there is noinfluence of these discharge signals, the counter voltage deviation isprevented.

In general, when the signal widths of the scanning signal and thedischarge signal are longer than a length, which is obtained bysubtracting a predetermined time (for example, 2 μs described above)from the length of 1 H, and shorter than the length of 1 H, thedischarge signal line Gs of each line may be connected to the scanningsignal line Gm behind six lines that is scanned after 3 H. When thesignal widths of the scanning signal and the discharge signal are longerthan a length, which is obtained by subtracting a predetermined timefrom (M+1) times (M is an integer of 0 or more) the length of 1 H, andshorter than (M+1) times the length of 1 H, the discharge signal line Gsof each line may be connected to the scanning signal line Gm behind(M+6) lines or more.

Hereinafter, the result of measuring the counter voltage deviation whenthe connection destination of the discharge signal line Gs connected tothe scanning signal line Gm of the rear line is changed will bedescribed.

FIG. 19 is a graph showing the relationship between the connectiondestination of the discharge signal line Gs_n and the optimum countervoltage difference. In the diagram, the horizontal axis indicates thescanning signal line Gm connected to the discharge signal line Gs_nthrough the signal-to-signal connection line Wsm, and the vertical axisindicates the optimum counter voltage difference (V). The optimumcounter voltage difference shown on the vertical axis is a differencebetween the optimum counter voltage for the subpixel SP1 of the pixelPn+3 and the optimum counter voltage for the subpixel SP1 of the pixelPn+2. The pixels Pn+2 and Pn+3 are included in two lines scannedsimultaneously. Here, the liquid crystal display device used for themeasurement is a full HD with a frame rate of 120 Hz, and themeasurement was performed for a case where the signal widths of thescanning signal and the discharge signal were the length of 1 H and thedisplayed gray scale was 64/255.

In the present Modification Example 4, the discharge signal for thepixel Pn+1 rises with a delay of 1 H from the falling edge of thescanning signal for the pixel Pn+2, and the discharge signal for thepixel Pn+2 rises with a delay of 2 H from the falling edge of thescanning signal for the pixel Pn+3. For this reason, for the subpixelelectrode 11 a of the subpixel SP1 of the pixel Pn+3, for example, whenGs_n is connected to Gm_n+4 (or Gm_n+6) and Gs_n+2 is connected toGm_n+6 (or Gm_n+8), basically no counter voltage deviation occurs.However, when Gs_n is connected to Gm_n+2 and Gs_n+2 is connected toGm_n+4, the falling of the scanning signal for the pixel Pn+3 and therising of the discharge signal for the pixel Pn+2 almost simultaneouslyoccur, and the optimum counter voltage decreases by 0.25 V.

On the other hand, for the subpixel electrode 11 a of the subpixel SP1of the pixel Pn+2, when the connection destination of the dischargesignal line Gs_n is changed to the scanning signal lines Gm_n+6, Gm_n+4,and Gm_n+2 (that is, when the connection destination of the dischargesignal line Gs_n+1 is changed to the scanning signal lines Gm_n+7,Gm_n+5, and Gm_n+3), the optimum counter voltage decreases by 0 V, 0.25V, and 1.40 V. That is, the above-described optimum counter voltagedifference is −1.15 V (difference between −1.40 V and −0.25 V describedabove) when the connection destination of the discharge signal line Gs_nis the scanning signal line Gm_n+2, the optimum counter voltagedifference decreases to −0.25 V when the connection destination of thedischarge signal line Gs_n is the scanning signal line Gm_n+4, and theoptimum counter voltage difference becomes 0 V corresponding to thetiming illustrated in FIG. 18 when the connection destination of thedischarge signal line Gs_n is the scanning signal line Gm_n+6, so thatthe counter voltage deviation is also eliminated.

As described above, according to the present Modification Example 4, thesignal widths of the scanning signal and the discharge signal are longerthan a length, which is obtained by subtracting the predetermined timeTd from (M+1) times (M is an integer of 0 or more) the length of 1 H,and shorter than (M+1) times the length of 1 H, and the discharge signalline Gs is connected to the scanning signal line Gm of a row, which isscanned after L horizontal scanning periods (L is M+3 or more, that is,3 or more), by the signal-to-signal connection line Wsm.

Therefore, since the discharge signal line Gs is connected to thescanning signal line Gm behind 2L lines, which is scanned after Lhorizontal scanning periods (L is an integer larger by 1 than the aboveN), it is possible to avoid the application of the discharge signal tothe gate electrode of the TFT 14 of the previous line within apredetermined time from the point in time at which no data signal isapplied to the subpixel electrodes 11 a and 11 b of the first subpixelSP1 and the second subpixel SP2 of each line. As a result, the countervoltage deviation is prevented.

In addition, according to Modification Example 4, the scanning signalline Gm and the signal-to-signal connection line Wsm are wired in theedge portion 101 c on one side of the liquid crystal panel 100 c, andthe signal-to-signal connection line Wsm intersects with the (2N−1) (=5)scanning signal lines Gm at the edge portion 101 c.

That is, the signal-to-signal connection line Wsm connects the dischargesignal line Gs and the scanning signal line Gm behind 2N lines, which isscanned after N(=3) horizontal scanning periods, to each other in aone-to-one manner, and the scanning signal is applied to the scanningsignal line Gm of each line from the edge portion 101 c side on whichthe signal-to-signal connection line Wsm is wired. Accordingly, thesignal-to-signal connection line Wsm and the (2N−1) scanning signallines Gm inevitably intersect with each other at the edge portion 101 con one side of the liquid crystal panel 100 c.

Modification Example 5

The scanning signal is separately applied to each scanning signal lineGm and each discharge signal line Gs is separately connected to the rearscanning signal line Gm in Embodiment 2 and Modification Example 4 ofEmbodiment 2, whereas the scanning signal lines Gm and Gm are connectedto each other and the discharge signal lines Gs and Gs are connected toeach other for two rows scanned simultaneously and the common scanningsignal is applied to the scanning signal lines Gm and Gm connected toeach other in Modification Example 5 of Embodiment 2.

FIG. 20 is a block diagram illustrating an example of the configurationof a liquid crystal display device according to Modification Example 5of Embodiment 2 of the present invention, and FIG. 21 is an explanatorydiagram illustrating a connection example of the signal-to-signalconnection line Wsm in a liquid crystal panel according to ModificationExample 5 of Embodiment 2. The liquid crystal display device accordingto the present Modification Example 5 includes a liquid crystal panel100 d, a gate driver GDc, a source driver SDb, and a display controlcircuit 4 d for controlling the display of the liquid crystal panel 100d using the gate driver GDc and the source driver SDb. Hereinafter, thesame configurations as in Embodiment 2 and Modification Example 4 ofEmbodiment 2 are denoted by the same reference numerals and the majorityof the description thereof will be omitted, and a configurationdifferent from Embodiment 2 and Modification Example 4 of Embodiment 2will be mainly described.

In the liquid crystal panel 100 d, for two lines scanned simultaneously,the scanning signal lines Gm and Gm are connected to each other by ascanning signal connection line Wmm, and the discharge signal lines Gsand Gs are connected to each other by a discharge signal connection lineWss. In an edge portion 101 d on one side of the liquid crystal panel100 d, a common scanning signal line Gmm for applying a common scanningsignal to the scanning signal connection line Wmm is separately wired.In addition, in the edge portion 101 d, the signal-to-signal connectionline Wsm connecting each discharge signal connection line Wss and thecommon scanning signal line Gmm, to which a scanning signal is appliedafter three horizontal scanning periods, to each other is separatelywired (refer to FIG. 21).

The display control circuit 4 d is different from the display controlcircuit 4 c in Embodiment 2 in that a scanning signal control circuit 42c controls one common scanning signal line Gmm every two rows of thematrix using the gate driver GDc.

In FIG. 21, similarly to the case of Modification Example 4, the pixel Pof the n-th line (n is a natural number), the scanning signal line Gm ofthe n-th line, and the discharge signal line Gs of the n-th line aredenoted by Pn, Gm_n, and Gs_n, respectively. The common scanning signalline common to the n-th line and the (n+1)-th line is denoted by Gmm_n.The omission of reference numerals and the display method of the TFTs 15a, 15 b, and 14 are the same as those in the case of FIG. 17 inModification Example 4. The signal-to-signal connection line Wsmintersects with two common scanning signal lines Gmm at the edge portion101 d of the liquid crystal panel 100 d.

As described above, according to the present Modification Example 5, thescanning signal lines Gm and Gm are connected to each other by thescanning signal connection line Wmm and the discharge signal lines Gsand Gs are connected to each other by the discharge signal connectionline Wss for two lines scanned simultaneously, and the common scanningsignal line Gmm for applying the scanning signal to the scanning signalconnection line Wmm and the signal-to-signal connection line Wsmconnecting the discharge signal connection line Wss and the scanningsignal connection line Wmm to each other are wired in the edge portion101 d of the liquid crystal panel 100 d. In addition, thesignal-to-signal connection line Wsm intersects with (N−1) commonscanning signal lines Gmm at the edge portion 101 d.

That is, the signal-to-signal connection line Wsm connects the dischargesignal connection line Wss and the scanning signal connection line Wmm,which makes a connection between two lines scanned after N (=3)horizontal scanning periods, to each other in a one-to-one manner, andthe scanning signal is applied to each common scanning signal line Gmmfrom the edge portion 101 d side on which the signal-to-signalconnection line Wsm is wired. Accordingly, the signal-to-signalconnection line Wsm and the (N−1) scanning signal lines Gmm inevitablyintersect with each other at the edge portion 101 d on one side of theliquid crystal panel 100 d.

It is to be noted that, as used herein and in the appended claims, thesingular forms “a”, “an”, and “the” include plural referents unless thecontext clearly dictates otherwise.

The embodiments disclosed this time are examples in all respects, andshould be considered to be not restrictive. The scope of the presentinvention is not limited to the above-described meaning but is indicatedby the claims, and it is intended that all modifications within themeaning and scope equivalent to the claims are included. In addition,the technical features described in the respective embodiments can becombined with each other.

1-10. (canceled)
 11. A liquid crystal display apparatus, comprising:pixels which are arranged in a matrix and each of which has at leastfirst and second subpixels defined to include an electrode pair of asubpixel electrode and a counter electrode facing each other with aliquid crystal layer interposed therebetween; first and second switchingelements for applying a data signal to subpixel electrodes included inthe first and second subpixels; a scanning signal line for applying ascanning signal for turning on the first and second switching elementsto control electrodes of the first and second switching elements foreach row of the matrix; an electrode pair of a discharge capacitorelectrode included in the second subpixel and a discharge capacitorcounter electrode connected to a predetermined potential; a thirdswitching element connected between the discharge capacitor electrodeand the subpixel electrode of the second subpixel; and a dischargesignal line for applying a discharge signal for turning on the thirdswitching element to a control electrode of the third switching elementfor each row of the matrix, wherein an on-period of one scanning signalfor turning on the first switching element included in one firstsubpixel and an on-period of one discharge signal applied to onedischarge signal line are not overlapped, a parasitic capacitance beingpresent between the one discharge signal line and the subpixel electrodeincluded in the one first subpixel.
 12. The liquid crystal displayapparatus according to claim 11, wherein a leading edge of the onedischarge signal is delayed by a predetermined time or more comparedwith a trailing edge of the one scanning signal.
 13. The liquid crystaldisplay apparatus according to claim 12, wherein the on-period of theone scanning signal is shorter than the length of one horizontalscanning period which is a time period from a time when the one scanningsignal rises to a time when a next scanning signal to rise next afterthe one scanning signal rises, further comprising a signal-to-signalconnection line connecting the one discharge signal line to a scanningsignal line to which a scanning signal to rise after N horizontalscanning periods (N is an integer of 1 or more) after the one scanningsignal rises is applied.
 14. The liquid crystal display apparatusaccording to claim 12, wherein the on-period of the one scanning signalis M times (M is an integer of 1 or more) the length of one horizontalscanning period or more and shorter than (M+1) times, the one horizontalscanning period being a time period from a time when the one scanningsignal rises to a time when a next scanning signal to rise next afterthe one scanning signal rises, further comprising a signal-to-signalconnection line connecting the one discharge signal line to a scanningsignal line to which a scanning signal to rise after N horizontalscanning periods (N is an integer of M+1 or more) after the one scanningsignal rises is applied.
 15. The liquid crystal display apparatusaccording to claim 11, wherein the first and second subpixels arearranged in a direction crossing the discharge signal line, and thedischarge signal line is arranged between adjacent first and secondsubpixels in pixels adjacent to each other in the direction.
 16. Theliquid crystal display apparatus according to claim 11, wherein thepolarity of a data signal applied to the first and second subpixels isinverted every frame period.
 17. The liquid crystal display apparatusaccording to claim 11, wherein each of the first and second subpixels isdefined to include an electrode pair of an auxiliary capacitor electrodeconnected to the subpixel electrode and an auxiliary capacitor counterelectrode connected to the predetermined potential.
 18. The liquidcrystal display apparatus according to claim 11, wherein the pixel isdefined to include an electrode pair having electrodes connected to thedischarge capacitor electrode and the subpixel electrode of the firstsubpixel.
 19. The liquid crystal display apparatus according to claim13, further comprising a liquid crystal panel comprising a displayregion where the pixels are arranged in a matrix, wherein the scanningsignal line extending from the display region and the signal-to-signalconnection line are wired in an edge portion of the liquid crystal panelexcluding the display region, and the signal-to-signal connection lineintersects with N scanning signal lines.
 20. The liquid crystal displayapparatus according to claim 14, further comprising a liquid crystalpanel comprising a display region where the pixels are arranged in amatrix, wherein the scanning signal line extending from the displayregion and the signal-to-signal connection line are wired in an edgeportion of the liquid crystal panel excluding the display region, andthe signal-to-signal connection line intersects with N scanning signallines.
 21. The liquid crystal display apparatus according to claim 13,further comprising, for each column of the matrix, two data signal linesincluding a first data signal line for applying data signals to pixelsin an odd row of the matrix and a second data signal line for applyingdata signals to pixels in an even row of the matrix, wherein twoadjacent rows are simultaneously scanned, further comprising a liquidcrystal panel comprising a display region where the pixels are arrangedin a matrix, wherein the scanning signal line extending from the displayregion and the signal-to-signal connection line are wired in an edgeportion of the liquid crystal panel excluding the display region, andthe signal-to-signal connection line intersects with 2N scanning signallines.
 22. The liquid crystal display apparatus according to claim 14,further comprising, for each column of the matrix, two data signal linesincluding a first data signal line for applying data signals to pixelsin an odd row of the matrix and a second data signal line for applyingdata signals to pixels in an even row of the matrix, wherein twoadjacent rows are simultaneously scanned, further comprising a liquidcrystal panel comprising a display region where the pixels are arrangedin a matrix, wherein the scanning signal line extending from the displayregion and the signal-to-signal connection line are wired in an edgeportion of the liquid crystal panel excluding the display region, andthe signal-to-signal connection line intersects with 2N scanning signallines.
 23. The liquid crystal display apparatus according to claim 13,further comprising, for each column of the matrix, two data signal linesincluding a first data signal line for applying data signals to pixelsin an odd row of the matrix and a second data signal line for applyingdata signals to pixels in an even row of the matrix, wherein twoadjacent rows are simultaneously scanned, further comprising: a scanningsignal connection line connecting scanning signal lines to each otherfor the two rows; a discharge signal connection line which connectsdischarge signal lines to each other for the two rows and is connectedto the signal-to-signal connection line; a common scanning signal linefor applying a scanning signal common to the two rows to the scanningsignal connection line; and a liquid crystal panel comprising a displayregion where the pixels are arranged in a matrix, wherein thesignal-to-signal connection line and the common scanning signal line arewired in an edge portion of the liquid crystal panel excluding thedisplay region, and the signal-to-signal connection line is wired incommon to the two rows, and intersects with N common scanning signallines.
 24. The liquid crystal display apparatus according to claim 14,further comprising, for each column of the matrix, two data signal linesincluding a first data signal line for applying data signals to pixelsin an odd row of the matrix and a second data signal line for applyingdata signals to pixels in an even row of the matrix, wherein twoadjacent rows are simultaneously scanned, further comprising: a scanningsignal connection line connecting scanning signal lines to each otherfor the two rows; a discharge signal connection line which connectsdischarge signal lines to each other for the two rows and is connectedto the signal-to-signal connection line; a common scanning signal linefor applying a scanning signal common to the two rows to the scanningsignal connection line; and a liquid crystal panel comprising a displayregion where the pixels are arranged in a matrix, wherein thesignal-to-signal connection line and the common scanning signal line arewired in an edge portion of the liquid crystal panel excluding thedisplay region, and the signal-to-signal connection line is wired incommon to the two rows, and intersects with N common scanning signallines.
 25. A driving method for driving a liquid crystal displayapparatus, the liquid crystal display apparatus comprising: pixels whichare arranged in a matrix and each of which has at least first and secondsubpixels defined to include an electrode pair of a subpixel electrodeand a counter electrode facing each other with a liquid crystal layerinterposed therebetween; first and second switching elements forapplying a data signal to subpixel electrodes included in the first andsecond subpixels; a scanning signal line for applying a scanning signalfor turning on the first and second switching elements to controlelectrodes of the first and second switching elements for each row ofthe matrix; an electrode pair of a discharge capacitor electrodeincluded in the second subpixel and a discharge capacitor counterelectrode connected to a predetermined potential; a third switchingelement connected between the discharge capacitor electrode and thesubpixel electrode of the second subpixel; and a discharge signal linefor applying a discharge signal for turning on the third switchingelement to a control electrode of the third switching element for eachrow of the matrix, the driving method comprising: applying the scanningsignal and the discharge signal so that an on-period of one scanningsignal for turning on the first switching element included in one firstsubpixel and an on-period of one discharge signal applied to onedischarge signal line are not overlapped, wherein a parasiticcapacitance is present between the one discharge signal line and thesubpixel electrode included in the one first subpixel.
 26. The drivingmethod according to claim 25, comprising: applying the scanning signaland the discharge signal so that a leading edge of the one dischargesignal is delayed by a predetermined time or more compared with atrailing edge of the one scanning signal.
 27. The driving methodaccording to claim 26, comprising applying, for each column of thematrix, the scanning signal having an on-period shorter than the lengthof one horizontal scanning period which is a time period from a timewhen the one scanning signal rises to a time when a next scanning signalto rise next after the one scanning signal rises; and applying, as theone discharge signal, a scanning signal which rises after N horizontalscanning periods (N is an integer of 1 or more) after the one scanningsignal rises.
 28. The driving method according to claim 26, comprisingapplying, for each column of the matrix, the scanning signal having anon-period which is M times (M is an integer of 1 or more) the length ofone horizontal scanning period or more and shorter than (M+1) times,wherein the one horizontal scanning period is a time period from a timewhen the one scanning signal rises to a time when a next scanning signalto rise next after the one scanning signal rises; and applying, as theone discharge signal, a scanning signal which rises after N horizontalscanning periods (N is an integer of M+1 or more) after the one scanningsignal rises.